The PCIe Link Status "Link Training" bit is only valid for functions
at the upstream end of a link, i.e., Root Ports, Downstream Ports, and
PCI-to-PCIe Bridges.
Signed-off-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
---
ls-caps.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/ls-caps.c b/ls-caps.c
index f192510..87b1a0d 100644
--- a/ls-caps.c
+++ b/ls-caps.c
@@ -786,11 +786,15 @@ static void cap_express_link(struct device *d, int where, int type)
FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
w = get_conf_word(d, where + PCI_EXP_LNKSTA);
- printf("\t\tLnkSta:\tSpeed %s, Width x%d, TrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
+ printf("\t\tLnkSta:\tSpeed %s, Width x%d, TrErr%c",
link_speed(w & PCI_EXP_LNKSTA_SPEED),
(w & PCI_EXP_LNKSTA_WIDTH) >> 4,
- FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
- FLAG(w, PCI_EXP_LNKSTA_TRAIN),
+ FLAG(w, PCI_EXP_LNKSTA_TR_ERR));
+ if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_DOWNSTREAM) ||
+ (type == PCI_EXP_TYPE_PCIE_BRIDGE))
+ printf(" Train%c",
+ FLAG(w, PCI_EXP_LNKSTA_TRAIN));
+ printf(" SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
--
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