Per PCIe spec r3.0, Table 7-16, the Retrain Link bit is writable but
always returns 0 when read, so decoding it gives no useful information.
Signed-off-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
---
ls-caps.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/ls-caps.c b/ls-caps.c
index 3b554fe..f192510 100644
--- a/ls-caps.c
+++ b/ls-caps.c
@@ -776,9 +776,8 @@ static void cap_express_link(struct device *d, int where, int type)
if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
(type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
- printf(" Disabled%c Retrain%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
+ printf(" Disabled%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
FLAG(w, PCI_EXP_LNKCTL_DISABLE),
- FLAG(w, PCI_EXP_LNKCTL_RETRAIN),
FLAG(w, PCI_EXP_LNKCTL_CLOCK),
FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
--
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