On Fri, May 17, 2013 at 6:15 PM, Phillip Susi <psusi@xxxxxxxxxx> wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > On 05/17/2013 07:52 PM, Bjorn Helgaas wrote: >> setpci will write whatever you tell it to; it doesn't check any >> constraints like "is ASPM supported?" But the Link Capabilities >> register is read-only per spec, so likely you won't be able to >> change that field, at least not by writing it directly. > > I assume it is RO according to the PCIe spec ( buggers seem to only > allow members of pcisig to download it ), but I checked the Intel > specs for the chip ( Sandybridge ) and it's RW. It looks like it > powers up as 00 and it's up to the bios to change it to advertise the > capability, and it seems Asus didn't bother with that. Right; I meant RO per the PCIe spec. If it's RW on your chip, setpci should be able to write it. >> You can always try using setpci to set the ASPM enable bits in the >> Link Control register on both the bridge and the device. When >> enabling, I think you're supposed to do the upstream end of the >> link first, then the downstream end (and the reverse for >> disabling). > > One thing I don't see anywhere is a status bit showing whether it > actually *is* in L0s or L1 currently, so how to know if it's working? I don't think software can actually tell -- those transitions are completely managed by hardware, and whenever the link is active, e.g., when you're accessing config space or transferring data, it would be in L0. If you can measure the power consumption, you might be able to see a difference there. I've seen people report that, but don't know how they do it. For example: https://lkml.kernel.org/r/CANUX_P3F5YhbZX3WGU-j1AGpbXb_T9Bis2ErhvKkFMtDvzatVQ@xxxxxxxxxxxxxx Bjorn -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
