-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 05/17/2013 07:52 PM, Bjorn Helgaas wrote: > setpci will write whatever you tell it to; it doesn't check any > constraints like "is ASPM supported?" But the Link Capabilities > register is read-only per spec, so likely you won't be able to > change that field, at least not by writing it directly. I assume it is RO according to the PCIe spec ( buggers seem to only allow members of pcisig to download it ), but I checked the Intel specs for the chip ( Sandybridge ) and it's RW. It looks like it powers up as 00 and it's up to the bios to change it to advertise the capability, and it seems Asus didn't bother with that. > You can always try using setpci to set the ASPM enable bits in the > Link Control register on both the bridge and the device. When > enabling, I think you're supposed to do the upstream end of the > link first, then the downstream end (and the reverse for > disabling). One thing I don't see anywhere is a status bit showing whether it actually *is* in L0s or L1 currently, so how to know if it's working? -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) Comment: Using GnuPG with undefined - http://www.enigmail.net/ iQEcBAEBAgAGBQJRlsgbAAoJEJrBOlT6nu75mVEIAIsgXJjpqx5BTaocW3fJdq/D 6uqBiZxrIiwzCxHcsxyyq2gf2z1cwV/SExb8KCtjycZjXha4Y4awa1ba+1H8QnUe YjLwRzsVSxlXUArwcUTrGQXsCYL5Q5IYejXAE0ki36Yfp5YvrKDLfuoKet76ROAY cIGY7w202o9jfCVVoc2nskwXWCOuTgdfffD3Kjhg5eLnB/SxcCfbIWvxw7pNmlW1 bmzBNg3Mbs/UpGSFoSAOKl2/gzniMtjej3iXEuPy/gp/BjrT9ijExlaE5s4gdxom 12GgHMO/+rtvXE0yz9+zD0oL3A8dLUW9cc1+pX6kjiSz6j7V7guRicNP1Zw4TLU= =VABF -----END PGP SIGNATURE----- -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
