On Tue, Mar 26, 2013 at 09:46:13PM +0100, Thomas Petazzoni wrote: > To me, the topology of the hardware is really that a single device > provides two features: the main interrupt controller and the MSI > interrupt controller. But I will adapt to whatever DT binding you > propose. No.. the HW is a single device that provides an interrupt on register write capability, so it ideally should be a single DT node.. The need to distinguish MSI vs IPI vs other usage is completely a side effect of how Linux's IRQ and PCI layers are hooked together today. > > I still wonder if the real solution shouldn't instead be to make the > > irq domain code MSI aware. For instance, you don't really need a > > cell to describe an interrupt because the interrupt number is Some kind of generic way for an irq chip driver to say 'here, I can provide some MSI interrupts' and then for the PCI layer to say 'irq layer, find me a driver that can provision a MSI with XXX properties' ? This need to stack an irq chip under a MSI is not something I think the kernel has had to support before, so new common code is probably needed... The interrupt chip should not need to know what the ultimate consumer of the interrupt capability will be, it just needs to tell the consumer 'write D to physical address A and irq I will trigger'. Jason -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
