On Tue, Feb 25, 2025 at 03:03:59PM +0530, Krishna Chaitanya Chundru wrote:
> Add a node for the TC956x PCIe switch, which has three downstream ports.
> Two embedded Ethernet devices are present on one of the downstream ports.
>
> Power to the TC956x is supplied through two LDO regulators, controlled by
> two GPIOs, which are added as fixed regulators. Configure the TC956x
> through I2C.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx>
> Reviewed-by: Bjorn Andersson <andersson@xxxxxxxxxx>
> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 116 +++++++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +-
> 2 files changed, 117 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> index 7a36c90ad4ec..13dbb24a3179 100644
> --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> @@ -218,6 +218,31 @@ vph_pwr: vph-pwr-regulator {
> regulator-min-microvolt = <3700000>;
> regulator-max-microvolt = <3700000>;
> };
> +
> + vdd_ntn_0p9: regulator-vdd-ntn-0p9 {
> + compatible = "regulator-fixed";
> + regulator-name = "VDD_NTN_0P9";
> + gpio = <&pm8350c_gpios 2 GPIO_ACTIVE_HIGH>;
> + regulator-min-microvolt = <899400>;
> + regulator-max-microvolt = <899400>;
> + enable-active-high;
> + pinctrl-0 = <&ntn_0p9_en>;
> + pinctrl-names = "default";
> + regulator-enable-ramp-delay = <4300>;
> + };
> +
> + vdd_ntn_1p8: regulator-vdd-ntn-1p8 {
> + compatible = "regulator-fixed";
> + regulator-name = "VDD_NTN_1P8";
> + gpio = <&pm8350c_gpios 3 GPIO_ACTIVE_HIGH>;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + enable-active-high;
> + pinctrl-0 = <&ntn_1p8_en>;
> + pinctrl-names = "default";
> + regulator-enable-ramp-delay = <10000>;
> + };
> +
> };
>
> &apps_rsc {
> @@ -735,6 +760,75 @@ &pcie1_phy {
> status = "okay";
> };
>
> +&pcie1_port {
> + pcie@0,0 {
> + compatible = "pci1179,0623", "pciclass,0604";
> + reg = <0x10000 0x0 0x0 0x0 0x0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + device_type = "pci";
> + ranges;
> + bus-range = <0x2 0xff>;
> +
> + vddc-supply = <&vdd_ntn_0p9>;
> + vdd18-supply = <&vdd_ntn_1p8>;
> + vdd09-supply = <&vdd_ntn_0p9>;
> + vddio1-supply = <&vdd_ntn_1p8>;
> + vddio2-supply = <&vdd_ntn_1p8>;
> + vddio18-supply = <&vdd_ntn_1p8>;
> +
> + i2c-parent = <&i2c0 0x77>;
> +
> + reset-gpios = <&pm8350c_gpios 1 GPIO_ACTIVE_LOW>;
> +
> + pcie@1,0 {
PCIe bus can be autodetected. Is there a reason for describing all the
ports and a full topology? If so, it should be stated in the commit
message.
> + reg = <0x20800 0x0 0x0 0x0 0x0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + device_type = "pci";
> + ranges;
> + bus-range = <0x3 0xff>;
> + };
> +
> + pcie@2,0 {
> + reg = <0x21000 0x0 0x0 0x0 0x0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + device_type = "pci";
> + ranges;
> + bus-range = <0x4 0xff>;
> + };
> +
> + pcie@3,0 {
--
With best wishes
Dmitry
