TC956x is the PCIe switch which has one upstream and three downstream ports. To one of the downstream ports ethernet MAC is connected as endpoint device. Other two downstream ports are supposed to connect to external device. One Host can connect to TC956x by upstream port. TC956x switch power is controlled by the GPIO's. After powering on the switch will immediately participate in the link training. if the host is also ready by that time PCIe link will established. The TC956x needs to configured certain parameters like de-emphasis, disable unused port etc before link is established. As the controller starts link training before the probe of pwrctl driver, the PCIe link may come up as soon as we power on the switch. Due to this configuring the switch itself through i2c will not have any effect as this configuration needs to done before link training. To avoid this introduce two functions in pci_ops to start_link() & stop_link() which will disable the link training if the PCIe link is not up yet. Enable global IRQ for PCIe controller so that recan can happen when link was up through global IRQ. This series depends on the https://lore.kernel.org/all/20250124101038.3871768-3-krishna.chundru@xxxxxxxxxxxxxxxx/ Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx> --- changes in v3: - The QPS615 PCIe switch is rebranded version of Toshiba switch TC956x. There is no difference between both the switches, both has two open downstream ports and one embedded downstream port to which Ethernet MAC is connected. As QPS615 is the rebranded version of Toshiba switch rename qps615 with tc956x so that this driver can be leveraged by all who are using Toshiba switch. - move common properties like l0s-delay, l1-delay and nfts to pci-host-common.yaml (bjorn H) - remove axi-clk-frequency property (Krzysztof) - Update the pattern properties (rob) - use pci-pci-bridge as the reference (rob) - change tx-amplitude-millivolt to tx-amplitude-microvolt (Krzysztof) - rename qps615_pwrctl_power_on to qps615_pwrctl_bring_up (Bart) - move the checks for l0s_delay, l1_delay etc to helper functon to reduce a level of indentation (bjorn H) - move platform_set_drvdata to end after there is no error return (bjorn H) - Replace GPIOD_ASIS to GPIOD_OUT_HIGH (mani) - Create a common api to check if link is up or not and use that to call stop_link() and start_link(). - couple of nits in comments, names etc from everyone Link to v3: https://lore.kernel.org/all/20241112-qps615_pwr-v3-3-29a1e98aa2b0@xxxxxxxxxxx/T/ Changes in v2: - As per offline discussions with rob i2c-parent is best suitable to use i2c client device. So use i2c-parent as suggested and remove i2c client node reference from the dt-bindings & devicetree. - Remove "PCI: Change the parent to correctly represent pcie hierarchy" as this requires seperate discussions. - Remove bdf logic to identify the dsp's and usp's to make it generic by using the logic that downstream devices will always child of upstream node and dsp1, dsp2 will always in same order (dmitry) - Remove recursive function for parsing devicetree instead parse only for required devicetree nodes (dmitry) - Fix the issue in be & le conversion (dmitry). - Call put_device for i2c device once done with the usage (dmitry) - Use $defs to describe common properties between upstream port and downstream properties. and remove unneccessary if then. (Krzysztof) - Place the qcom,qps615 compatibility in dt-binding document in alphabatic order (Krzysztof) - Rename qcom,no-dfe to describe it as hardware capability and change qcom,nfts description to reflect hardware details (Krzysztof) - Fix the indentation in the example in dt binding (dmitry) - Add more description to qcom,nfts (dmitry) - Remove nanosec from the property description (dmitry) - Link to v2: https://lore.kernel.org/r/linux-arm-msm/20240803-qps615-v2-0-9560b7c71369@xxxxxxxxxxx/T/ Changes in v1: - Instead of referencing whole i2c-bus add i2c-client node and reference it (Dmitry) - Change the regulator's as per the schematics as per offline review (bjorn Andresson) - Remove additional host check in bus.c (Bart) - For stop_link op change return type from int to void (Bart) - Remove firmware based approach for configuring sequence as suggested by multiple reviewers. - Introduce new dt-properties for the switch to configure the switch as we are replacing the firmware based approach. - The downstream ports add properties in the child nodes which will represented in PCIe hierarchy format. - Removed D3cold D0 sequence in suspend resume for now as it needs separate discussion. - Link to v1: https://lore.kernel.org/linux-pci/20240626-qps615-v1-4-2ade7bd91e02@xxxxxxxxxxx/T/ --- Krishna Chaitanya Chundru (9): arm64: dts: qcom: qcs6490-rb3gen2: Add TC956x PCIe switch node PCI: Add new start_link() & stop_link function ops PCI: dwc: Add host_start_link() & host_start_link() hooks for dwc glue drivers PCI: dwc: Implement .start_link(), .stop_link() hooks PCI: qcom: Add support for host_stop_link() & host_start_link() PCI: PCI: Add pcie_is_link_active() to determine if the PCIe link is active PCI: pwrctrl: Add power control driver for tc956x dt-bindings: PCI: qcom,pcie-sc7280: Add 'global' interrupt arm64: dts: qcom: sc7280: Add 'global' interrupt to the PCIe RC nodes Krishna chaitanya chundru (1): dt-bindings: PCI: Add binding for Toshiba TC956x PCIe switch .../devicetree/bindings/pci/qcom,pcie-sc7280.yaml | 8 +- .../devicetree/bindings/pci/toshiba,tc956x.yaml | 178 ++++++ arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 116 ++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 7 +- drivers/pci/controller/dwc/pcie-designware-host.c | 18 + drivers/pci/controller/dwc/pcie-designware.h | 16 + drivers/pci/controller/dwc/pcie-qcom.c | 35 ++ drivers/pci/hotplug/pciehp_hpc.c | 13 +- drivers/pci/pci.c | 26 +- drivers/pci/pwrctrl/Kconfig | 6 + drivers/pci/pwrctrl/Makefile | 1 + drivers/pci/pwrctrl/pci-pwrctrl-tc956x.c | 625 +++++++++++++++++++++ include/linux/pci.h | 7 + 13 files changed, 1035 insertions(+), 21 deletions(-) --- base-commit: 09fbf3d502050282bf47ab3babe1d4ed54dd1fd8 change-id: 20250212-qps615_v4_1-f8e62fa11786 Best regards, -- Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx>
