On Fr, 2025-02-21 at 09:37 +0800, Inochi Amaoto wrote:
> Add support for DesignWare-based PCIe controller in SG2044 SoC.
>
> Signed-off-by: Inochi Amaoto <inochiama@xxxxxxxxx>
> ---
> drivers/pci/controller/dwc/Kconfig | 10 +
> drivers/pci/controller/dwc/Makefile | 1 +
> drivers/pci/controller/dwc/pcie-dw-sophgo.c | 282 ++++++++++++++++++++
> 3 files changed, 293 insertions(+)
> create mode 100644 drivers/pci/controller/dwc/pcie-dw-sophgo.c
>
[...]
> diff --git a/drivers/pci/controller/dwc/pcie-dw-sophgo.c b/drivers/pci/controller/dwc/pcie-dw-sophgo.c
> new file mode 100644
> index 000000000000..a4ca4f1e26e0
> --- /dev/null
> +++ b/drivers/pci/controller/dwc/pcie-dw-sophgo.c
> @@ -0,0 +1,282 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * PCIe host controller driver for Sophgo SoCs.
> + *
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/gpio/consumer.h>
> +#include <linux/irqchip/chained_irq.h>
> +#include <linux/irqdomain.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/phy/phy.h>
> +#include <linux/property.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
Drop this ...
> +
> +#include "pcie-designware.h"
> +
> +#define to_sophgo_pcie(x) dev_get_drvdata((x)->dev)
> +
> +#define PCIE_INT_SIGNAL 0xc48
> +#define PCIE_INT_EN 0xca0
> +
> +#define PCIE_SIGNAL_INTX_SHIFT 5
> +
> +#define PCIE_INT_EN_INTX_SHIFT 1
> +#define PCIE_INT_EN_INT_SII BIT(0)
> +#define PCIE_INT_EN_INT_INTA BIT(1)
> +#define PCIE_INT_EN_INT_INTB BIT(2)
> +#define PCIE_INT_EN_INT_INTC BIT(3)
> +#define PCIE_INT_EN_INT_INTD BIT(4)
> +#define PCIE_INT_EN_INT_MSI BIT(5)
> +
> +struct sophgo_pcie {
> + struct dw_pcie pci;
> + void __iomem *app_base;
> + struct clk_bulk_data *clks;
> + unsigned int clk_cnt;
> + struct reset_control *rst;
... and this. It is unused.
regards
Philipp
