Sophgo's SG2044 SoC uses Synopsys Designware PCIe core to implement RC mode. For legacy interrupt, the PCIe controller on SG2044 implement its own legacy interrupt controller. For MSI/MSI-X, it use an external interrupt controller to handle. The external MSI interrupt controller patch can be found on [1]. As SG2044 needs a mirror change to support the way to send MSI message and different irq number. [1] https://lore.kernel.org/all/cover.1736921549.git.unicorn_wang@xxxxxxxxxxx/ Inochi Amaoto (2): dt-bindings: pci: Add Sophgo SG2044 PCIe host PCI: sophgo-dwc: Add Sophgo SG2044 PCIe driver .../bindings/pci/sophgo,sg2044-pcie.yaml | 125 ++++++++ drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-dw-sophgo.c | 282 ++++++++++++++++++ 4 files changed, 418 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2044-pcie.yaml create mode 100644 drivers/pci/controller/dwc/pcie-dw-sophgo.c -- 2.48.1
