On Fri, Feb 14, 2025 at 11:48:16PM +0800, Hans Zhang wrote: > > > On 2025/2/14 23:31, Manivannan Sadhasivam wrote: > > On Fri, Feb 14, 2025 at 10:28:11PM +0800, Hans Zhang wrote: > > > Sorry Mani, I shouldn't have spread this SOC bug. This is a bug in RTL > > > design, the WSTRB signal of AXI bus is not connected correctly, so the first > > > generation SOC cannot send message, because we mainly use RC mode, and we > > > cannot send PME_Turn_OFF, that is, our SOC does not support L2. I have no > > > choice about this, I entered the company relatively late, and our SOC has > > > already TO. > > > > Ok. Just to clear my head, this patch is needed irrespective of the hw issue, > > right? And with or without this patch, first revision hw cannot send any MSG > > TLPs? > > Yes, that was a problem with our own SOC design, the Cadence RTL bug. > > > If so, it is fine. But is there a way we could detect those first generation IPs > > and flag it to users about broken MSG TLP support? Atleast, that would make the > > users aware of broken hw. > > I don't know how to do it, but here are the questions that were actually > tested. > Not related to this patch, but please check if it is possible to detect those controllers. > > > > > > This patch is to solve the Cadence common code bug, and does not conform to > > > Cadence documentation. > > > > you mean 'does'? > > > > What I mean is that common code bit16=1 is to send a message without data, > while Cadence's development document says that bit16=0 is to send a message > without data. This is not consistent with the documentation description, and > the final verification results, the development documentation described is > correct. > Ok, makes sense now. - Mani -- மணிவண்ணன் சதாசிவம்
