On Fri, Feb 07, 2025 at 06:39:23PM +0800, Hans Zhang wrote:
> View from cdns document cdn_pcie_gen4_hpa_axi_ips_ug_v1.04.pdf.
> In section 9.1.7.1 AXI Subordinate to PCIe Address Translation
> Registers below:
>
> axi_s_awaddr bits 16 is 1 for MSG with data and 0 for MSG without data.
>
> Signed-off-by: hans.zhang <18255117159@xxxxxxx>
> ---
> Changes since v1-v2:
> - Change email number and Signed-off-by
> ---
> drivers/pci/controller/cadence/pcie-cadence-ep.c | 3 +--
> drivers/pci/controller/cadence/pcie-cadence.h | 2 +-
> 2 files changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> index e0cc4560dfde..0bf4cde34f51 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> @@ -352,8 +352,7 @@ static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, u8 intx,
> spin_unlock_irqrestore(&ep->lock, flags);
>
> offset = CDNS_PCIE_NORMAL_MSG_ROUTING(MSG_ROUTING_LOCAL) |
> - CDNS_PCIE_NORMAL_MSG_CODE(msg_code) |
> - CDNS_PCIE_MSG_NO_DATA;
> + CDNS_PCIE_NORMAL_MSG_CODE(msg_code);
> writel(0, ep->irq_cpu_addr + offset);
> }
>
> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
> index f5eeff834ec1..39ee9945c903 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence.h
> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
> @@ -246,7 +246,7 @@ struct cdns_pcie_rp_ib_bar {
> #define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8)
> #define CDNS_PCIE_NORMAL_MSG_CODE(code) \
> (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK)
> -#define CDNS_PCIE_MSG_NO_DATA BIT(16)
> +#define CDNS_PCIE_MSG_DATA BIT(16)
Oops! So how did you spot the issue? Did INTx triggering ever worked? RC should
have reported it as malformed TLP isn't it?
- Mani
--
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