On Fri, Feb 07, 2025 at 06:46:22PM +0000, Wilson Ding wrote: > > > > -----Original Message----- > > From: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> > > Sent: Friday, February 7, 2025 9:58 AM > > To: Wilson Ding <dingwei@xxxxxxxxxxx>; cassel@xxxxxxxxxx > > Cc: Bjorn Helgaas <helgaas@xxxxxxxxxx>; lpieralisi@xxxxxxxxxx; > > thomas.petazzoni@xxxxxxxxxxx; kw@xxxxxxxxx; robh@xxxxxxxxxx; > > bhelgaas@xxxxxxxxxx; linux-pci@xxxxxxxxxxxxxxx; linux-arm- > > kernel@xxxxxxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; Sanghoon Lee > > <salee@xxxxxxxxxxx> > > Subject: [EXTERNAL] Re: [PATCH 1/1] PCI: armada8k: Add link-down handle > > > > + Niklas (who was interested in link down handling) On Sat, Feb 01, 2025 > > + at 11: 05: 56PM +0000, Wilson Ding wrote: > > On November 13, 2024 3: > > + 02: 55 AM GMT+05: 30, Bjorn Helgaas > > <mailto: helgaas@ kernel. org> > > + wrote: > > > > > > + Niklas (who was interested in link down handling) > > > > On Sat, Feb 01, 2025 at 11:05:56PM +0000, Wilson Ding wrote: > > > > On November 13, 2024 3:02:55 AM GMT+05:30, Bjorn Helgaas > > > > <mailto:helgaas@xxxxxxxxxx> wrote: > > > > >In subject: > > > > > > > > > > PCI: armada8k: Add link-down handling > > > > > > > > > >On Mon, Nov 11, 2024 at 10:48:13PM -0800, Jenishkumar Maheshbhai > > > > Patel wrote: > > > > >> In PCIE ISR routine caused by RST_LINK_DOWN we schedule work to > > > > >> handle the link-down procedure. > > > > >> Link-down procedure will: > > > > >> 1. Remove PCIe bus > > > > >> 2. Reset the MAC > > > > >> 3. Reconfigure link back up > > > > >> 4. Rescan PCIe bus > > > > > > > > > >s/PCIE/PCIe/ > > > > > > > > > >Rewrap to fill 75 columns. > > > > > > > > > >I assume this basically removes a Root Port (and the hierarchy > > > > >below > > > > >it) if the link goes down, and then resets the MAC and tries to > > > > >bring up the link and enumerate the hierarchy again. > > > > > > > > > >No other drivers do this, so why does armada8k need it? Is this to > > > > >work around some unreliable link? > > > > > > > > Certainly Qcom IPs have this same feature and I was also looking to > > > > implement it. But the link down should not be handled by this in the > > controller driver. > > > > > > > > Instead, it should be tied to bus reset in the core and the reset > > > > should be done through a callback implemented in the controller > > > > drivers. This way, the reset cannot happen in the back of PCI core and client > > drivers. > > > > > > > > That said, the Link down IRQ received by this driver should also be > > > > propagated back to the PCI core and the core should then call the > > > > callback to reset the bus that I mentioned above. > > > > > > > > > > It's more than a work-around for the unreliable link. A few customers > > > may have such application - independent power supply to the device > > > with dedicated reset GPIO to #PRST. In this way, the power cycle and > > > warm reset of RC and EP won't have impact on each other. However, it > > > may lead into the PCI driver not aware of the link down when an unexpected > > power down or reset occurs on the device. > > > We cannot assume the link will be recovered soon. The worse thing is > > > the driver may continue access to the device, which may hang the bus. > > > Since the device is no longer present on the bus, it's better to > > > remove it. Besides, in order to bring up the link, the only way is to > > > reset the MAC, which starts over the state machine of LTSSM. > > > > > > Well, we also noticed that there is no other driver that did this. I > > > agree it is not necessary if the power cycle or warm reset of the > > > device is done gracefully. The user can remove the device prior to the > > > power cycle/reset. And do the rescan after the link is recovered. However, > > the unexpected power down is still possible. > > > Please enlighten me if there is any better approach to handle such > > > unexpected link down. > > > > > > > There is no issue in retraining the link. My concern is that, the retrain should > > not happen autonomously in the controller driver. PCI core should be made > > informed of it. More below. > > > > Do you mean > - pass the link down/up events to PCI core > - remove the device or hierarchy by PCI core upon link down > - initiate the link retraining in PCI core by calling the platform retrain callbacks > - rescan the bus once link is recovered > Yeah. This is what I came up with quickly: ``` diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index b6536ed599c3..561eeb464220 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -706,6 +706,33 @@ void pci_free_host_bridge(struct pci_host_bridge *bridge) } EXPORT_SYMBOL(pci_free_host_bridge); +void pci_host_bridge_handle_link_down(struct pci_host_bridge *bridge) +{ + struct pci_bus *bus = bridge->bus; + struct pci_dev *child, *tmp; + int ret; + + pci_lock_rescan_remove(); + + /* Knock the devices off bus since we cannot access them */ + list_for_each_entry_safe(child, tmp, &bus->devices, bus_list) + pci_stop_and_remove_bus_device(child); + + /* Now retrain the link in a controller specific way to bring it back */ + if (bus->ops->retrain_link) { + ret = bus->ops->retrain_link(bus); + if (ret) { + dev_err(&bridge->dev, "Failed to retrain the link!\n"); + pci_unlock_rescan_remove(); + return; + } + } + + pci_rescan_bus(bus); + pci_unlock_rescan_remove(); +} +EXPORT_SYMBOL(pci_host_bridge_handle_link_down); + /* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */ static const unsigned char pcix_bus_speed[] = { PCI_SPEED_UNKNOWN, /* 0 */ diff --git a/include/linux/pci.h b/include/linux/pci.h index 47b31ad724fa..1c6f18a51bdd 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -637,6 +637,7 @@ struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, size_t priv); void pci_free_host_bridge(struct pci_host_bridge *bridge); +void pci_host_bridge_handle_link_down(struct pci_host_bridge *bridge); struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); void pci_set_host_bridge_release(struct pci_host_bridge *bridge, @@ -804,6 +805,7 @@ struct pci_ops { void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); + int (*retrain_link)(struct pci_bus *bus); }; /* ``` Your controller driver has to call pci_host_bridge_handle_link_down() during the link down event (make it threaded if not done already). Then you should also populate the pci_ops::retrain_link() callback with the function that retrains the broken link. Finally, the bus will be rescanned to enumerate the devices. I do have plans to plug this retrain callback to one of the bus_reset() functions in the future so that we can bring the link back while doing bus level reset (uncorrectable AERs and such). But this will do the job for now. I will send a series on Monday with Qcom driver as a reference. - Mani -- மணிவண்ணன் சதாசிவம்
