On Wed, Jan 15, 2025 at 03:06:37PM +0800, Chen Wang wrote: > From: Chen Wang <unicorn_wang@xxxxxxxxxxx> > > Add binding for Sophgo SG2042 PCIe host controller. > + sophgo,link-id: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: | > + SG2042 uses Cadence IP, every IP is composed of 2 cores (called link0 > + & link1 as Cadence's term). Each core corresponds to a host bridge, > + and each host bridge has only one root port. Their configuration > + registers are completely independent. SG2042 integrates two Cadence IPs, > + so there can actually be up to four host bridges. "sophgo,link-id" is > + used to identify which core/link the PCIe host bridge node corresponds to. IIUC, the registers of Cadence IP 1 and IP 2 are completely independent, and if you describe both of them, you would have separate "pcie@62000000" stanzas with separate 'reg' and 'ranges' properties.
