On Monday 16 December 2024 14:15:26 Rostyslav Khudolii wrote: > Hi all, > > I am currently working on a custom AMD Ryzen™ Embedded R2000 (AMD > Family 17h) device and have discovered that PCI IO Extended > Configuration Space (ECS) access is no longer possible. > > Consider the following functions: amd_bus_cpu_online() and > pci_enable_pci_io_ecs(). These functions are part of the > amd_postcore_init() initcall and are responsible for enabling PCI IO > ECS. Both functions modify the CoreMasterAccessCtrl (EnableCf8ExtCfg) > value via the PCI device function or the MSR register directly (see > the "BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h", > Section 2.7). However, neither the MSR register nor the PCI function > at the specified address (D18F3x8C) exists for AMD Family 17h. The > CoreMasterAccessCtrl register still exists but is now located at a > different address (see the "Processor Programming Reference (PPR) for > AMD Family 17h", Section 2.1.8). > > I would be happy to submit a patch to fix this issue. However, since > the most recent change affecting this functionality appears to be 14 > years old, I would like to confirm whether this is still relevant or > if the kernel should always be built with CONFIG_PCI_MMCONFIG when ECS > access is required. > > Linux Kernel info: > > root@qt5222:~# uname -a > Linux qt5222 6.6.49-2447-qtec-standard--gef032148967a #1 SMP Fri Nov > 22 09:25:55 UTC 2024 x86_64 GNU/Linux > > Best regards, > Ros Hello, For a longer time I have patches for pciutils project which allows to query PCIe devices via this AMD ECS I/O API. lspci provides more options how to query PCI and PCIe devices and one option is raw cf8/cfc I/O access (via ioport/iopl syscalls), which is useful for debugging purposes. The disadvantage is that this method provides access only to PCI registers. And that is why this AMD ECS I/O API can be useful as it extends lspci raw cf8/cfc I/O to access also PCIe registers. My implementation in those lspci patches follows the linux kernel logic, but for unknown reason it do not want to work. Upper cf8 (ECS) bits are ignored when accessing register value via cfc. Filip retested it today on AMD 19h family machine, that it really does not work. Now when I found and read this Rostyslav's email I understood why it does not work. Rostyslav, I would like to ask you, do you have patches / updates for enabling the EnableCf8ExtCfg bit for AMD 17h+ family? I could try to adjust my lspci changes for new machines. Anyway, if you are interesting in lspci patches for my WIP AMD ECS, I can send them. Pali
