On Tue, 14 Jan 2025 17:49:44 -0600
"Bowman, Terry" <terry.bowman@xxxxxxx> wrote:
> On 1/14/2025 5:38 PM, Ira Weiny wrote:
> > Bowman, Terry wrote:
> >>
> >>
> >> On 1/14/2025 4:02 PM, Ira Weiny wrote:
> >>> Terry Bowman wrote:
> >>>> Add logic to map CXL PCIe Upstream Switch Port (USP) RAS registers.
> >>>>
> >>>> Introduce 'struct cxl_regs' member into 'struct cxl_port' to cache a
> >>>> pointer to the CXL Upstream Port's mapped RAS registers.
> >>>>
> >>>> Also, introduce cxl_uport_init_ras_reporting() to perform the USP RAS
> >>>> register mapping. This is similar to the existing
> >>>> cxl_dport_init_ras_reporting() but for USP devices.
> >>>>
> >>>> The USP may have multiple downstream endpoints. Before mapping AER
> >>>> registers check if the registers are already mapped.
> >>>>
> >>>> Signed-off-by: Terry Bowman <terry.bowman@xxxxxxx>
> >>>> ---
> >>>> drivers/cxl/core/pci.c | 15 +++++++++++++++
> >>>> drivers/cxl/cxl.h | 4 ++++
> >>>> drivers/cxl/mem.c | 8 ++++++++
> >>>> 3 files changed, 27 insertions(+)
> >>>>
> >>>> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> >>>> index 1af2d0a14f5d..97e6a15bea88 100644
> >>>> --- a/drivers/cxl/core/pci.c
> >>>> +++ b/drivers/cxl/core/pci.c
> >>>> @@ -773,6 +773,21 @@ static void cxl_disable_rch_root_ints(struct cxl_dport *dport)
> >>>> writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND);
> >>>> }
> >>>>
> >>>> +void cxl_uport_init_ras_reporting(struct cxl_port *port)
> >>>> +{
> >>>> + /* uport may have more than 1 downstream EP. Check if already mapped. */
> >>>> + if (port->uport_regs.ras)
> >>>> + return;
> >>>> +
> >>>> + port->reg_map.host = &port->dev;
> >>>> + if (cxl_map_component_regs(&port->reg_map, &port->uport_regs,
> >>>> + BIT(CXL_CM_CAP_CAP_ID_RAS))) {
> >>>> + dev_err(&port->dev, "Failed to map RAS capability.\n");
> >>>> + return;
> >>> Why return here? Actually I think 8/16 had the same issue now that I see
> >>> this.
> >>>
> >>> Other than that:
> >>>
> >>> Reviewed-by: Ira Weiny <ira.weiny@xxxxxxxxx>
> >>>
> >>> [snip]
> >> If RAS registers fail mapping then exit to avoid CXL Port error handler initialization.
> >> The CXL Port error handlers rely on RAS registers for logging and without mapped RAS
> >> registers the error handlers will return immediately.
> > Sorry I was not clear and I should not have clipped the text so much. You
> > return in a block which is at the end of the function:
> >
> >
> > +void cxl_uport_init_ras_reporting(struct cxl_port *port)
> > +{
> > + /* uport may have more than 1 downstream EP. Check if already mapped. */
> > + if (port->uport_regs.ras)
> > + return;
> > +
> > + port->reg_map.host = &port->dev;
> > + if (cxl_map_component_regs(&port->reg_map, &port->uport_regs,
> > + BIT(CXL_CM_CAP_CAP_ID_RAS))) {
> > + dev_err(&port->dev, "Failed to map RAS capability.\n");
> > + return;
> > + }
> > +}
> >
> > So no need for this specific statement?
> >
> > Ira
>
> I wrote it this way to add the handler initialization (after the return) in later patch
> without a diff removal. But, your correct, I can remove the 'return' statement in this patch
> and add in later patch without cluttering the diff.
>
> Thanks. I'll make the change.
>
Leave it as it stands. I'm sure Ira doesn't mind given the additions later.
I'd prefer we keep things clean across the series.
Jonathan
> Regards,
> Terry
>
>
>
