On Fri, Jan 03, 2025 at 08:10:17PM +0530, Anand Moon wrote: > Hi Niklas > > On Fri, 3 Jan 2025 at 19:55, Niklas Cassel <cassel@xxxxxxxxxx> wrote: > > > > Hello Anand, > > > > On Fri, Jan 03, 2025 at 07:24:07PM +0530, Anand Moon wrote: > > > > > > Thanks for testing this patch. > > > > > > This patch should have been tested on hardware that includes all the > > > relevant controllers, > > > such as PCI 2.0, PCI 3.0, and the SATA controller. > > > I will test this patch again on all the Radxa devices I have. > > > > > > This patch's dependency lies in deferring the probe until the PHY > > > controller initializes. > > > > > > CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=m > > > > > > Note that the splat, as reported in this thread, and in: > > https://lore.kernel.org/netdev/20250101235122.704012-1-francesco@xxxxxxxx/T/ > > > > is related to the network PHY (CONFIG_REALTEK_PHY) on the RTL8125 NIC, > > which is connected to one of the PCIe Gen2 controllers, not the PCIe PHY > > on the PCIe controller (CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) itself. > > > > For the record, I run with all the relevant drivers as built-in: > > CONFIG_PCIE_ROCKCHIP_DW_HOST=y > > CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y (for the PCIe Gen2 controllers) > > CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y (for the PCIe Gen3 controllers) > > CONFIG_R8169=y > > CONFIG_REALTEK_PHY=y > > > > > > > > > > To my surprise, we have not enabled mdio on Rock-5B boards. > > > can you check if these changes work on your end? > > > > I think these changes are wrong, at least for rock5b. > > We need to enable the GMAC PHY and reset it using the proper GPIO pin > (PCIE_PERST_L). > Please refer to the schematic for more details. The PERST# GPIO is already asserted + deasserted from the PCIe Root Complex (host) driver: https://github.com/torvalds/linux/blob/v6.13-rc5/drivers/pci/controller/dwc/pcie-dw-rockchip.c#L191-L206 which will cause the endpoint device (a RTL8125 NIC in this case) to be reset during bootup. Kind regards, Niklas
