Hi Niklas On Fri, 3 Jan 2025 at 19:55, Niklas Cassel <cassel@xxxxxxxxxx> wrote: > > Hello Anand, > > On Fri, Jan 03, 2025 at 07:24:07PM +0530, Anand Moon wrote: > > > > Thanks for testing this patch. > > > > This patch should have been tested on hardware that includes all the > > relevant controllers, > > such as PCI 2.0, PCI 3.0, and the SATA controller. > > I will test this patch again on all the Radxa devices I have. > > > > This patch's dependency lies in deferring the probe until the PHY > > controller initializes. > > > > CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=m > > > Note that the splat, as reported in this thread, and in: > https://lore.kernel.org/netdev/20250101235122.704012-1-francesco@xxxxxxxx/T/ > > is related to the network PHY (CONFIG_REALTEK_PHY) on the RTL8125 NIC, > which is connected to one of the PCIe Gen2 controllers, not the PCIe PHY > on the PCIe controller (CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) itself. > > For the record, I run with all the relevant drivers as built-in: > CONFIG_PCIE_ROCKCHIP_DW_HOST=y > CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y (for the PCIe Gen2 controllers) > CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y (for the PCIe Gen3 controllers) > CONFIG_R8169=y > CONFIG_REALTEK_PHY=y > > > > > > To my surprise, we have not enabled mdio on Rock-5B boards. > > can you check if these changes work on your end? > > I think these changes are wrong, at least for rock5b. We need to enable the GMAC PHY and reset it using the proper GPIO pin (PCIE_PERST_L). Please refer to the schematic for more details. These changes also apply to other device tree nodes for different boards. Thanks -Anand > > On rock5b the RTL8125 NIC is connected via PCI, and PCI devices should not > be specified in device tree, as PCI is a bus that can be enumerated. > > > > > > -----8<----------8<----------8<----------8<----------8<----------8<----- > > alarm@rock-5b:/media/nvme0/mainline/linux-rockchip-6.y-devel$ git diff > > arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts > > b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts > > index c44d001da169..5008a05efd2a 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts > > +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts > > @@ -155,6 +155,19 @@ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { > > }; > > }; > > > > +&mdio1 { > > + rgmii_phy1: ethernet-phy@1 { > > + /* RTL8211F */ > > + compatible = "ethernet-phy-id001c.c916"; > > + reg = <0x1>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&rtl8211f_rst>; > > + reset-assert-us = <20000>; > > + reset-deassert-us = <100000>; > > + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; > > + }; > > +}; > > + > > &combphy0_ps { > > status = "okay"; > > }; > > @@ -224,6 +237,21 @@ &hdptxphy_hdmi0 { > > status = "okay"; > > }; > > > > +&gmac1 { > > + clock_in_out = "output"; > > + phy-handle = <&rgmii_phy1>; > > + phy-mode = "rgmii"; > > + pinctrl-0 = <&gmac1_miim > > + &gmac1_tx_bus2 > > + &gmac1_rx_bus2 > > + &gmac1_rgmii_clk > > + &gmac1_rgmii_bus>; > > + pinctrl-names = "default"; > > + tx_delay = <0x3a>; > > + rx_delay = <0x3e>; > > + status = "okay"; > > +}; > > + > > &i2c0 { > > pinctrl-names = "default"; > > pinctrl-0 = <&i2c0m2_xfer>; > > @@ -419,6 +447,12 @@ pcie3_vcc3v3_en: pcie3-vcc3v3-en { > > }; > > }; > > > > + rtl8211f { > > + rtl8211f_rst: rtl8211f-rst { > > + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; > > + }; > > + }; > > + > > usb { > > vcc5v0_host_en: vcc5v0-host-en { > > rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; > > > > > > Kind regards, > > > Niklas > > > > Can you check this on your end > > > > alarm@rock-5b:~$ sudo cat /sys/kernel/debug/devices_deferred > > [sudo] password for alarm: > > fc400000.usb dwc3: failed to initialize core > > alarm@rock-5b:~$ sudo cat /sys/kernel/debug/devices_deferred > > Sure: > # cat /sys/kernel/debug/devices_deferred > fc400000.usb dwc3: failed to initialize core > > > Kind regards, > Niklas
