On Wed, 11 Dec 2024 17:39:56 -0600 Terry Bowman <terry.bowman@xxxxxxx> wrote: > Add logic to map CXL PCIe Upstream Switch Port (USP) RAS registers. > > Introduce 'struct cxl_regs' member into 'struct cxl_port' to cache a > pointer to the CXL Upstream Port's mapped RAS registers. > > Also, introduce cxl_uport_init_ras_reporting() to perform the USP RAS > register mapping. This is similar to the existing > cxl_dport_init_ras_reporting() but for USP devices. > > The USP may have multiple downstream endpoints. Before mapping AER > registers check if the registers are already mapped. > > Signed-off-by: Terry Bowman <terry.bowman@xxxxxxx> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
