On Wed, 11 Dec 2024 17:39:55 -0600 Terry Bowman <terry.bowman@xxxxxxx> wrote: > The CXL mem driver (cxl_mem) currently maps and caches a pointer to RAS > registers for the endpoint's Root Port. The same needs to be done for > each of the CXL Downstream Switch Ports and CXL Root Ports found between > the endpoint and CXL Host Bridge. > > Introduce cxl_init_ep_ports_aer() to be called for each CXL Port in the > sub-topology between the endpoint and the CXL Host Bridge. This function > will determine if there are CXL Downstream Switch Ports or CXL Root Ports > associated with this Port. The same check will be added in the future for > upstream switch ports. > > Move the RAS register map logic from cxl_dport_map_ras() into > cxl_dport_init_ras_reporting(). This eliminates the need for the helper > function, cxl_dport_map_ras(). Could possibly do that as a precursor. > > cxl_init_ep_ports_aer() calls cxl_dport_init_ras_reporting() to map > the RAS registers for CXL Downstream Switch Ports and CXL Root Ports. > > cxl_dport_init_ras_reporting() must check for previously mapped registers > before mapping. This is necessary because endpoints under a CXL switch > may share CXL Downstream Switch Ports or CXL Root Ports. Ensure the port > registers are only mapped once. > > Signed-off-by: Terry Bowman <terry.bowman@xxxxxxx> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
