Hi Mani, > -----Original Message----- > From: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> > Sent: Monday, December 9, 2024 3:25 PM > To: Havalige, Thippeswamy <thippeswamy.havalige@xxxxxxx> > Cc: Bjorn Helgaas <helgaas@xxxxxxxxxx>; bhelgaas@xxxxxxxxxx; > lpieralisi@xxxxxxxxxx; kw@xxxxxxxxx; robh@xxxxxxxxxx; krzk+dt@xxxxxxxxxx; > conor+dt@xxxxxxxxxx; linux-pci@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux- > kernel@xxxxxxxxxxxxxxx; jingoohan1@xxxxxxxxx; Simek, Michal > <michal.simek@xxxxxxx>; Gogada, Bharat Kumar > <bharat.kumar.gogada@xxxxxxx> > Subject: RE: [PATCH 2/2] PCI: amd-mdb: Add AMD MDB Root Port driver > > > > On December 9, 2024 3:14:15 PM GMT+05:30, "Havalige, Thippeswamy" > <thippeswamy.havalige@xxxxxxx> wrote: > >Hi Sadhasivam, > > > >> -----Original Message----- > >> From: manivannan.sadhasivam@xxxxxxxxxx > >> <manivannan.sadhasivam@xxxxxxxxxx> > >> Sent: Sunday, December 8, 2024 6:29 PM > >> To: Havalige, Thippeswamy <thippeswamy.havalige@xxxxxxx> > >> Cc: Bjorn Helgaas <helgaas@xxxxxxxxxx>; bhelgaas@xxxxxxxxxx; > >> lpieralisi@xxxxxxxxxx; kw@xxxxxxxxx; robh@xxxxxxxxxx; > >> krzk+dt@xxxxxxxxxx; > >> conor+dt@xxxxxxxxxx; linux-pci@xxxxxxxxxxxxxxx; > >> conor+devicetree@xxxxxxxxxxxxxxx; linux- > >> kernel@xxxxxxxxxxxxxxx; jingoohan1@xxxxxxxxx; Simek, Michal > >> <michal.simek@xxxxxxx>; Gogada, Bharat Kumar > >> <bharat.kumar.gogada@xxxxxxx> > >> Subject: Re: [PATCH 2/2] PCI: amd-mdb: Add AMD MDB Root Port driver > >> > >> On Mon, Dec 02, 2024 at 08:21:36AM +0000, Havalige, Thippeswamy wrote: > >> > >> [...] > >> > >> > > > + d = irq_domain_get_irq_data(pcie->mdb_domain, irq); > >> > > > + if (intr_cause[d->hwirq].str) > >> > > > + dev_warn(dev, "%s\n", intr_cause[d->hwirq].str); > >> > > > + else > >> > > > + dev_warn(dev, "Unknown IRQ %ld\n", d->hwirq); > >> > > > + > >> > > > + return IRQ_HANDLED; > >> > > > >> > > I see that some of these messages are > >> > > "Correctable/Non-Fatal/Fatal error message"; I assume this Root > >> > > Port doesn't have an AER Capability, and this interrupt is the > >> > > "System Error" controlled by the Root Control Error Enable bits > >> > > in > >> the > >> > > PCIe Capability? (See PCIe r6.0, sec 6.2.6) > >> > > > >> > > Is there any way to hook this into the AER handling so we can do > >> > > something > >> about > >> > > it, since the devices *below* the Root Port may support AER and > >> > > may have > >> useful > >> > > information logged? > >> > > > >> > > Since this is DWC-based, I suppose these are general questions > >> > > that apply to all the similar drivers. > >> > > >> > > >> > Thanks for review, We have this in our plan to hook platform > >> > specific error > >> interrupts > >> > to AER in future will add this support. > >> > > >> > >> So on your platform, AER (also PME) interrupts are reported over SPI > >> interrupt only and not through MSI/MSI-X? Most of the DWC controllers > >> have this weird behavior of reporting AER/PME only through SPI, but > >> that should be legacy controllers. Newer ones does support MSI. > > > >Thanks for your comment, Yes our platform supports platform specific > >Error Interrupts over SPI. > > > > My question was specifically about whether your platform _only_ supports SPI or > both SPI and MSI for AER/PME. Yes, our platform supports AER/PME over both MSI and SPI. > > - Mani > > மணிவண்ணன் சதாசிவம் Regards, Thippeswamy H
