On Mon, Nov 18, 2024 at 09:04:54AM +0100, Lorenzo Bianconi wrote:
> Replace clk_bulk_prepare() and clk_bulk_enable() with
> clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up() routine.
>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>
> Signed-off-by: Lorenzo Bianconi <lorenzo@xxxxxxxxxx>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
- Mani
> ---
> drivers/pci/controller/pcie-mediatek-gen3.c | 14 +++-----------
> 1 file changed, 3 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
> index 4d1c797a32c236faf79428eb8a83708e9c4f21d8..3cfcb45d31508142d28d338ff213f70de9b4e608 100644
> --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> @@ -948,12 +948,6 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)
> pm_runtime_enable(dev);
> pm_runtime_get_sync(dev);
>
> - err = clk_bulk_prepare(pcie->num_clks, pcie->clks);
> - if (err) {
> - dev_err(dev, "failed to prepare clock\n");
> - goto err_clk_prepare;
> - }
> -
> val = FIELD_PREP(PCIE_VAL_LN0_DOWNSTREAM, 0x47) |
> FIELD_PREP(PCIE_VAL_LN1_DOWNSTREAM, 0x47) |
> FIELD_PREP(PCIE_VAL_LN0_UPSTREAM, 0x41) |
> @@ -966,17 +960,15 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)
> FIELD_PREP(PCIE_K_FINETUNE_MAX, 0xf);
> writel_relaxed(val, pcie->base + PCIE_PIPE4_PIE8_REG);
>
> - err = clk_bulk_enable(pcie->num_clks, pcie->clks);
> + err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks);
> if (err) {
> dev_err(dev, "failed to prepare clock\n");
> - goto err_clk_enable;
> + goto err_clk_prepare_enable;
> }
>
> return 0;
>
> -err_clk_enable:
> - clk_bulk_unprepare(pcie->num_clks, pcie->clks);
> -err_clk_prepare:
> +err_clk_prepare_enable:
> pm_runtime_put_sync(dev);
> pm_runtime_disable(dev);
> reset_control_assert(pcie->mac_reset);
>
> --
> 2.47.0
>
--
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