On Wed, Oct 02, 2024 at 03:09:26PM -0500, Bjorn Helgaas wrote:
> On Wed, Oct 02, 2024 at 01:12:23PM -0500, Bjorn Helgaas wrote:
> > On Tue, Oct 01, 2024 at 07:05:18PM +0530, Ajay Agarwal wrote:
> > > The current sequence in the driver for L1ss update is as follows.
> > >
> > > Disable L1ss
> > > Disable L1
> > > Enable L1ss as required
> > > Enable L1 if required
> > >
> > > PCIe spec r6.2, section 5.5.4, recommends that setting either
> > > or both of the enable bits for ASPM L1 PM Substates must be done
> > > while ASPM L1 is disabled. My interpretation here is that
> > > clearing L1ss should also be done when L1 is disabled. Thereby,
> > > change the sequence as follows.
> > >
> > > Disable L1
> > > Disable L1ss
> > > Enable L1ss as required
> > > Enable L1 if required
> > ...
>
> > pcie_config_aspm_link() has a comment ("Spec 2.0 ...") about the
> > configuration order, but I'd like to update that, add a section
> > reference, and make sure we do the disable in the right order.
>
> Found some language about this in the ASPM Control description in PCIe
> r6.2, sec 7.5.3.7, Link Control.
>
Right. Added in the next version.
> Also in sec 7.9.9.3, Root Complex Link Control, although I don't think
> Linux has any support for this register.
Right. There is no support for this reg.
