Hi,
On 8/12/24 16:43, Jim Quinlan wrote:
> On Fri, Aug 9, 2024 at 5:53 AM Stanimir Varbanov <svarbanov@xxxxxxx> wrote:
>>
>> Hi Jim,
>>
>> On 8/1/24 01:28, Jim Quinlan wrote:
>>> The 7712 SOC adds a software init reset device for the PCIe HW.
>>> If found in the DT node, use it.
>>>
>>> Signed-off-by: Jim Quinlan <james.quinlan@xxxxxxxxxxxx>
>>> ---
>>> drivers/pci/controller/pcie-brcmstb.c | 19 +++++++++++++++++++
>>> 1 file changed, 19 insertions(+)
>>>
>>> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
>>> index 4d68fe318178..948fd4d176bc 100644
>>> --- a/drivers/pci/controller/pcie-brcmstb.c
>>> +++ b/drivers/pci/controller/pcie-brcmstb.c
>>> @@ -266,6 +266,7 @@ struct brcm_pcie {
>>> struct reset_control *rescal;
>>> struct reset_control *perst_reset;
>>> struct reset_control *bridge_reset;
>>> + struct reset_control *swinit_reset;
>>> int num_memc;
>>> u64 memc_size[PCIE_BRCM_MAX_MEMC];
>>> u32 hw_rev;
>>> @@ -1633,12 +1634,30 @@ static int brcm_pcie_probe(struct platform_device *pdev)
>>> if (IS_ERR(pcie->bridge_reset))
>>> return PTR_ERR(pcie->bridge_reset);
>>>
>>> + pcie->swinit_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "swinit");
>>> + if (IS_ERR(pcie->swinit_reset))
>>> + return PTR_ERR(pcie->swinit_reset);
>>> +
>>> ret = clk_prepare_enable(pcie->clk);
>>> if (ret)
>>> return dev_err_probe(&pdev->dev, ret, "could not enable clock\n");
>>>
>>> pcie->bridge_sw_init_set(pcie, 0);
>>>
>>> + if (pcie->swinit_reset) {
>>> + ret = reset_control_assert(pcie->swinit_reset);
>>> + if (dev_err_probe(&pdev->dev, ret, "could not assert reset 'swinit'\n"))
>>> + goto clk_disable_unprepare;
>>> +
>>> + /* HW team recommends 1us for proper sync and propagation of reset */
>>> + udelay(1);
>>
>> Hmm, shouldn't this delay be part of .assert/.deassert reset_control
>> driver? I think this detail is reset-control hw specific and the
>> consumers does not need to know it.
>
> This was discussed previously. I pointed out that we use a reset
Sorry, I missed that discussion.
> provider that governs dozens of devices. The only thing that the
> provider could do is to employ a worst case delay used for all
> resets. This is unacceptable; we have certain devices that may have
> to invoke
> reset often and require timely action, and we do not want them having
> to wait the same amount of worst case delay as for example, a UART device reset.
>
> Further, if I do a "grep reset_control_assert -A 10 drivers" I see
> plenty of existing drivers that use usleep/msleep/udelay after the call to
> reset_control_assert, just as I am doing now.
Yes, I saw them.
>
> As far as my opinion goes (FWIW) I think the delay is more apt to
> be present in the consumer driver and not the provider driver. To
> ascertain this specific delay I had to consult with the PCIe HW team,
> not the HW team that implemented the reset controller.
>
Thank you for the explanation!
~Stan
