Hi Manivannan, Bjorn On Wed, 7 Aug 2024 at 22:30, Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> wrote: > > On Wed, Aug 07, 2024 at 11:31:06AM -0500, Bjorn Helgaas wrote: > > On Tue, Jun 25, 2024 at 09:27:57PM +0530, Anand Moon wrote: > > > Rockchip PCIe driver lets waits for the combo PHY link like PCIe 3.0, > > > PCIe 2.0 and SATA 3.0 controller to be up during the probe this > > > consumes several milliseconds during boot. > > > > This needs some wordsmithing. "driver lets waits" ... I guess "lets" > > is not supposed to be there? I'm not sure what the relevance of "PCIe > > 3.0, PCIe 2.0, SATA 3.0" is. I assume the host controller driver > > doesn't know what downstream devices might be present, and the async > > probing is desirable no matter what they might be? > > Ok I will improve this commit message. Rockchip DWC PCIe driver currently waits for the combo PHY link (PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established during the probe, which could consume several milliseconds during boot. To optimize boot time, this commit allows asynchronous probing. This change enables the PCIe link establishment to occur in the background while other devices are being probed. > > Since the DWC driver is enabling link training during boot, it also waits for > the link to be 'up'. But if the device is 'up', then the wait time would be > usually negligible (few ms). But if there is no device, then the wait time of 1s > would be evident. > > But here the patch is trying to avoid the few ms delay itself (which is fine). > The type of endpoint might have some impact on the link training also. But async > probe is always preferred. > > - Mani > Ok, Thanks -Anand
