On Tue, Jun 25, 2024 at 09:27:57PM +0530, Anand Moon wrote:
> Rockchip PCIe driver lets waits for the combo PHY link like PCIe 3.0,
> PCIe 2.0 and SATA 3.0 controller to be up during the probe this
> consumes several milliseconds during boot.
This needs some wordsmithing. "driver lets waits" ... I guess "lets"
is not supposed to be there? I'm not sure what the relevance of "PCIe
3.0, PCIe 2.0, SATA 3.0" is. I assume the host controller driver
doesn't know what downstream devices might be present, and the async
probing is desirable no matter what they might be?
> Establishing a PCIe link can take a while; allow asynchronous probing so
> that link establishment can happen in the background while other devices
> are being probed.
>
> Signed-off-by: Anand Moon <linux.amoon@xxxxxxxxx>
> ---
> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> index 61b1acba7182..74a3e9d172a0 100644
> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> @@ -367,6 +367,7 @@ static struct platform_driver rockchip_pcie_driver = {
> .name = "rockchip-dw-pcie",
> .of_match_table = rockchip_pcie_of_match,
> .suppress_bind_attrs = true,
> + .probe_type = PROBE_PREFER_ASYNCHRONOUS,
> },
> .probe = rockchip_pcie_probe,
> };
> --
> 2.44.0
>
