On Thu, Jul 25, 2024 at 04:29:56PM -0400, Jim Quinlan wrote: > On Thu, Jul 25, 2024 at 12:53 AM Manivannan Sadhasivam > <manivannan.sadhasivam@xxxxxxxxxx> wrote: > > > > On Tue, Jul 16, 2024 at 05:31:24PM -0400, Jim Quinlan wrote: > > > Previously, our chips provided three inbound "BARS" with fixed purposes: > > > the first was for mapping SoC internal registers, the second was for > > > memory, and the third was for memory but with the endian swapped. We > > > typically only used one of these BARs. > > > > > > Complicating that BARs usage was the fact that the PCIe HW would do a > > > baroque internal mapping of system memory, and concatenate the regions of > > > multiple memory controllers. > > > > > > Newer chips such as the 7712 and Cable Modem SOCs have taken a step forward > > > and now provide multiple inbound BARs. This works in concert with the > > > dma-ranges property, where each provided range becomes an inbound BAR. > > > > > > This commit provides support for these new chips and their multiple > > > inbound BARs but also keeps the legacy support for the older system. > > > > > > > BAR belongs to the endpoints not to the RC. How can the RC have 'BARs'? RC can > > only map endpoint BARs to MEM region. What you are referring to is 'MEM region' > > maybe? > > Agreed, it is confusing. Long story short, the HW team gave the > inbound windows the label "BAR". We will still have to use their > register names, Wow, such an inventive naming :) > e.g. PCIE_MISC_RC_BAR4_CONFIG_LO, but what I can do is change > for example "struct rc_bar" to "struct inbound_win" as well as make similar > changes to the code and function names. > > Let's assume you will be okay with my plan above; if not, please tell > me what you would prefer. > Yes please. Just keep BAR in the register name and use 'inbound_win' elsewhere. Even better, add a comment at the top of these register names to clarify that these refer to inbound windows. - Mani -- மணிவண்ணன் சதாசிவம்
