On Tue, Jul 16, 2024 at 05:31:21PM -0400, Jim Quinlan wrote:
> Our HW design has again changed a register offset which used to be standard
Changed for which SoC? Please mention that this is a preparatory work.
> for all Broadcom SOCs with PCIe cores. This difference is now reconciled
> for the registers HARD_DEBUG and INTR2_CPU_BASE.
>
> Signed-off-by: Jim Quinlan <james.quinlan@xxxxxxxxxxxx>
With that,
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
- Mani
> Reviewed-by: Stanimir Varbanov <svarbanov@xxxxxxx>
> Reviewed-by: Florian Fainelli <florian.fainelli@xxxxxxxxxxxx>
> ---
> drivers/pci/controller/pcie-brcmstb.c | 39 ++++++++++++++++-----------
> 1 file changed, 24 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> index 4dc2ff7f3167..073d790d97b7 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -122,7 +122,6 @@
> #define PCIE_MEM_WIN0_LIMIT_HI(win) \
> PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
>
> -#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
> #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
> #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK 0x200000
> #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
> @@ -131,9 +130,9 @@
> (PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK | \
> PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK)
>
> -#define PCIE_INTR2_CPU_BASE 0x4300
> #define PCIE_MSI_INTR2_BASE 0x4500
> -/* Offsets from PCIE_INTR2_CPU_BASE and PCIE_MSI_INTR2_BASE */
> +
> +/* Offsets from INTR2_CPU and MSI_INTR2 BASE offsets */
> #define MSI_INT_STATUS 0x0
> #define MSI_INT_CLR 0x8
> #define MSI_INT_MASK_SET 0x10
> @@ -184,9 +183,11 @@
> #define SSC_STATUS_PLL_LOCK_MASK 0x800
> #define PCIE_BRCM_MAX_MEMC 3
>
> -#define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
> -#define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
> -#define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
> +#define IDX_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_INDEX])
> +#define DATA_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_DATA])
> +#define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->reg_offsets[RGR1_SW_INIT_1])
> +#define HARD_DEBUG(pcie) ((pcie)->reg_offsets[PCIE_HARD_DEBUG])
> +#define INTR2_CPU_BASE(pcie) ((pcie)->reg_offsets[PCIE_INTR2_CPU_BASE])
>
> /* Rescal registers */
> #define PCIE_DVT_PMU_PCIE_PHY_CTRL 0xc700
> @@ -205,6 +206,8 @@ enum {
> RGR1_SW_INIT_1,
> EXT_CFG_INDEX,
> EXT_CFG_DATA,
> + PCIE_HARD_DEBUG,
> + PCIE_INTR2_CPU_BASE,
> };
>
> enum {
> @@ -651,7 +654,7 @@ static int brcm_pcie_enable_msi(struct brcm_pcie *pcie)
> BUILD_BUG_ON(BRCM_INT_PCI_MSI_LEGACY_NR > BRCM_INT_PCI_MSI_NR);
>
> if (msi->legacy) {
> - msi->intr_base = msi->base + PCIE_INTR2_CPU_BASE;
> + msi->intr_base = msi->base + INTR2_CPU_BASE(pcie);
> msi->nr = BRCM_INT_PCI_MSI_LEGACY_NR;
> msi->legacy_shift = 24;
> } else {
> @@ -898,12 +901,12 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> /* Take the bridge out of reset */
> pcie->bridge_sw_init_set(pcie, 0);
>
> - tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
> + tmp = readl(base + HARD_DEBUG(pcie));
> if (is_bmips(pcie))
> tmp &= ~PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
> else
> tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
> - writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
> + writel(tmp, base + HARD_DEBUG(pcie));
> /* Wait for SerDes to be stable */
> usleep_range(100, 200);
>
> @@ -1072,7 +1075,7 @@ static void brcm_config_clkreq(struct brcm_pcie *pcie)
> }
>
> /* Start out assuming safe mode (both mode bits cleared) */
> - clkreq_cntl = readl(pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
> + clkreq_cntl = readl(pcie->base + HARD_DEBUG(pcie));
> clkreq_cntl &= ~PCIE_CLKREQ_MASK;
>
> if (strcmp(mode, "no-l1ss") == 0) {
> @@ -1115,7 +1118,7 @@ static void brcm_config_clkreq(struct brcm_pcie *pcie)
> dev_err(pcie->dev, err_msg);
> mode = "safe";
> }
> - writel(clkreq_cntl, pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
> + writel(clkreq_cntl, pcie->base + HARD_DEBUG(pcie));
>
> dev_info(pcie->dev, "clkreq-mode set to %s\n", mode);
> }
> @@ -1337,9 +1340,9 @@ static void brcm_pcie_turn_off(struct brcm_pcie *pcie)
> writel(tmp, base + PCIE_MISC_PCIE_CTRL);
>
> /* Turn off SerDes */
> - tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
> + tmp = readl(base + HARD_DEBUG(pcie));
> u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
> - writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
> + writel(tmp, base + HARD_DEBUG(pcie));
>
> /* Shutdown PCIe bridge */
> pcie->bridge_sw_init_set(pcie, 1);
> @@ -1425,9 +1428,9 @@ static int brcm_pcie_resume_noirq(struct device *dev)
> pcie->bridge_sw_init_set(pcie, 0);
>
> /* SERDES_IDDQ = 0 */
> - tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
> + tmp = readl(base + HARD_DEBUG(pcie));
> u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
> - writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
> + writel(tmp, base + HARD_DEBUG(pcie));
>
> /* wait for serdes to be stable */
> udelay(100);
> @@ -1499,12 +1502,16 @@ static const int pcie_offsets[] = {
> [RGR1_SW_INIT_1] = 0x9210,
> [EXT_CFG_INDEX] = 0x9000,
> [EXT_CFG_DATA] = 0x9004,
> + [PCIE_HARD_DEBUG] = 0x4204,
> + [PCIE_INTR2_CPU_BASE] = 0x4300,
> };
>
> static const int pcie_offsets_bmips_7425[] = {
> [RGR1_SW_INIT_1] = 0x8010,
> [EXT_CFG_INDEX] = 0x8300,
> [EXT_CFG_DATA] = 0x8304,
> + [PCIE_HARD_DEBUG] = 0x4204,
> + [PCIE_INTR2_CPU_BASE] = 0x4300,
> };
>
> static const struct pcie_cfg_data generic_cfg = {
> @@ -1539,6 +1546,8 @@ static const int pcie_offset_bcm7278[] = {
> [RGR1_SW_INIT_1] = 0xc010,
> [EXT_CFG_INDEX] = 0x9000,
> [EXT_CFG_DATA] = 0x9004,
> + [PCIE_HARD_DEBUG] = 0x4204,
> + [PCIE_INTR2_CPU_BASE] = 0x4300,
> };
>
> static const struct pcie_cfg_data bcm7278_cfg = {
> --
> 2.17.1
>
--
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