Hi Jim, On 7/3/24 21:02, Jim Quinlan wrote: > Our HW design has again changed a register offset which used to be standard > for all Broadcom SOCs with PCIe cores. This difference is now reconciled > for the registers HARD_DEBUG and INTR2_CPU_BASE. > > Signed-off-by: Jim Quinlan <james.quinlan@xxxxxxxxxxxx> > --- > drivers/pci/controller/pcie-brcmstb.c | 33 +++++++++++++++++---------- > 1 file changed, 21 insertions(+), 12 deletions(-) > > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c > index 59daa4b2e6c5..d8c0f1474369 100644 > --- a/drivers/pci/controller/pcie-brcmstb.c > +++ b/drivers/pci/controller/pcie-brcmstb.c > @@ -122,7 +122,6 @@ > #define PCIE_MEM_WIN0_LIMIT_HI(win) \ > PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8) > > -#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 > #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2 > #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK 0x200000 > #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 > @@ -131,9 +130,9 @@ > (PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK | \ > PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK) > > -#define PCIE_INTR2_CPU_BASE 0x4300 > #define PCIE_MSI_INTR2_BASE 0x4500 > -/* Offsets from PCIE_INTR2_CPU_BASE and PCIE_MSI_INTR2_BASE */ > + > +/* Offsets from INTR2_CPU and MSI_INTR2 BASE offsets */ > #define MSI_INT_STATUS 0x0 > #define MSI_INT_CLR 0x8 > #define MSI_INT_MASK_SET 0x10 > @@ -187,6 +186,8 @@ > #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX]) > #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA]) > #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1]) > +#define HARD_DEBUG(pcie) (pcie->reg_offsets[PCIE_HARD_DEBUG]) > +#define INTR2_CPU_BASE(pcie) (pcie->reg_offsets[PCIE_INTR2_CPU_BASE]) > Drop the tab before HARD_DEBUG & INTR2_CPU_BASE. Also checkpatch should complain about missing brackets around pcie: #define HARD_DEBUG(pcie) ((pcie)->reg_offsets[PCIE_HARD_DEBUG]) ~Stan
