On Fri, May 25, 2012 at 3:58 PM, H. Peter Anvin <hpa@xxxxxxxxx> wrote:
> On 05/25/2012 02:55 PM, Bjorn Helgaas wrote:
>>
>> I think we actually have a separate bug here. On 64-bit non-x86
>> architectures, PCIBIOS_MAX_MEM_32 is a 64-bit -1, so the following
>> attempt to avoid putting a 32-bit BAR above 4G only works on x86,
>> where PCIBIOS_MAX_MEM_32 is 0xffffffff.
>>
>> /* don't allocate too high if the pref mem doesn't support 64bit*/
>> if (!(res->flags & IORESOURCE_MEM_64))
>> max = PCIBIOS_MAX_MEM_32;
>>
>> I think we should fix this with a separate patch that removes
>> PCIBIOS_MAX_MEM_32 altogether, replacing this use with an explicit
>> 0xffffffff (or some other "max 32-bit value" symbol). I don't think
>> there's anything arch-specific about this.
>>
>> So I'd like to see two patches here:
>> 1) Avoid allocating 64-bit regions for 32-bit BARs
>> 2) Try to allocate regions above 4GB for 64-bit BARs
>
> Do we also need to track the maximum address available to the CPU?
We are allocating from the resources available on this bus, which
means the host bridge apertures or a subset. If the arch supplies
those, that should be enough. If it doesn't, we default to
iomem_resource. On x86, we trim that down to only the supported
address space:
iomem_resource.end = (1ULL << boot_cpu_data.x86_phys_bits) - 1;
But I'm sure some other architectures don't do that yet. I guess
that's one of the risks -- if an arch is doesn't tell us the apertures
and doesn't trim iomem_resource, we could allocate a non-addressable
region.
Bjorn
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