On Mon, May 06, 2024 at 01:28:21PM -0700, Dave Jiang wrote: > > > On 5/6/24 12:27 PM, Adam Manzanares wrote: > > Hello all, > > > > I would like to have a discussion with the CXL development community about > > current outstanding issues and also invite developers interested in RAS and > > memory tiering to participate. > > > > The first topic I believe we should discuss is how we can ensure as a group > > that we are prioritizing upstream work. On a recent upstream CXL development > > discussion call there was a call to review more work. I apologize for not > > grabbing the link, but I believe Dave Jiang is leveraging patchwork and this > > link should be shared with others so we can help get more reviews where needed. > > Bundle for the potential fixes > https://patchwork.kernel.org/bundle/cxllinux/cxl-fixes/ > > Bundle for the next merge window > https://patchwork.kernel.org/bundle/cxllinux/cxl-next/ > > Just be aware patchwork only takes patches, so the bundle are registered with the first patch of a series. The listing does display the origin series. Thanks Dave, much appreciated. We will leverage this and I will spread the message about how important it is to review. > > DJ > > > > > The second topic I would like to discuss is how we integrate RAS features that > > have similar equivalents in the kernel. A CXL device can provide info about > > memory media errors in a similar fashion to memory controllers that have EDAC > > support. Discussions have been put on the list and I would like to hear thoughts > > from the community about where this should go [1]. On the same topic CXL has > > port level RAS features and the PCIe DW series touched on this issue [2] > > > > The third topic I would like to discuss is how we can get a set of common > > benchmarks for memory tiering evaluations. Our team has done some initial > > work in this space, but we want to hear more from end users about their > > workloads of concern. There was a proposal related to this topic, but from what > > I understand no meeting has been held [3]. > > > > The last topic that I believe is worth discussion is how do we come up with > > a baseline for testing. I am aware of 3 efforts that could be used cxl_test, > > qemu, and uunit testing framework [4]. > > > > Apologies for getting this out late, and please include anyone that may be > > interested in joining a discussion. > > > > [1] https://lore.kernel.org/linux-cxl/20240417075053.3273543-1-ruansy.fnst@xxxxxxxxxxx/ > > [2] https://lore.kernel.org/lkml/20231130115044.53512-1-shradha.t@xxxxxxxxxxx/ > > [3] https://lore.kernel.org/all/2b29dd3d-bb2c-6a8c-94d2-d5c2e035516a@xxxxxxxxxx > > [4] https://lore.kernel.org/linux-cxl/170795677066.3697776.12587812713093908173.stgit@ubuntu/ >
