On 5/8/24 1:16 AM, Devi Priya wrote:
On 5/1/2024 9:58 AM, Alexandru Gagniuc wrote:
There are four PCIe ports on IPQ9574, pcie0 thru pcie3. This series
addresses pcie2, which is a gen3x2 port. The board I have only uses
pcie2, and that's the only one enabled in this series. pcie3 is added
as a special request, but is untested.
I believe this makes sense as a monolithic series, as the individual
pieces are not that useful by themselves.
Hi Alexandru,
As Dmitry suggested, we are working on enabling the PCIe NOC clocks
via Interconnect. We will be posting the PCIe series with
Interconnect support [1] shortly.
I am generally very hesitant to depend on unmerged series, as this can
cause undue delays. In this particular case, I considered that both
series can continue to stay independent, with the ability to convert the
PCIe users to the new clock scheme when the time is right.
[1] -
https://lore.kernel.org/linux-arm-msm/20240430064214.2030013-1-quic_varada@xxxxxxxxxxx/
What changes would be needed to this series to make use of this? How
does one use the "interconnected" clocks?
Alex
Thanks,
S.Devi Priya
In v2, I've had some issues regarding the dt schema checks. For
transparency, I used the following test invocations to test:
make dt_binding_check
DT_SCHEMA_FILES=qcom,pcie.yaml:qcom,ipq8074-qmp-pcie-phy.yaml
make dtbs_check
DT_SCHEMA_FILES=qcom,pcie.yaml:qcom,ipq8074-qmp-pcie-phy.yaml
Changes since v3:
- "const"ify .hw.init fields for the PCIE pipe clocks
- Used pciephy_v5_regs_layout instead of v4 in phy-qcom-qmp-pcie.c
- Included Manivannan's patch for qcom-pcie.c clocks
- Dropped redundant comments in "ranges" and "interrupt-map" of pcie2.
- Added pcie3 and pcie3_phy dts nodes
- Moved snoc and anoc clocks to PCIe controller from PHY
Changes since v2:
- reworked resets in qcom,pcie.yaml to resolve dt schema errors
- constrained "reg" in qcom,pcie.yaml
- reworked min/max intems in qcom,ipq8074-qmp-pcie-phy.yaml
- dropped msi-parent for pcie node, as it is handled by "msi" IRQ
Changes since v1:
- updated new tables in phy-qcom-qmp-pcie.c to use lowercase hex
numbers
- reorganized qcom,ipq8074-qmp-pcie-phy.yaml to use a single list of
clocks
- reorganized qcom,pcie.yaml to include clocks+resets per compatible
- Renamed "pcie2_qmp_phy" label to "pcie2_phy"
- moved "ranges" property of pcie@20000000 higher up
Alexandru Gagniuc (7):
dt-bindings: clock: Add PCIe pipe related clocks for IPQ9574
clk: qcom: gcc-ipq9574: Add PCIe pipe clocks
dt-bindings: PCI: qcom: Add IPQ9574 PCIe controller
PCI: qcom: Add support for IPQ9574
dt-bindings: phy: qcom,ipq8074-qmp-pcie: add ipq9574 gen3x2 PHY
phy: qcom-qmp-pcie: add support for ipq9574 gen3x2 PHY
arm64: dts: qcom: ipq9574: add PCIe2 and PCIe3 nodes
Manivannan Sadhasivam (1):
PCI: qcom: Switch to devm_clk_bulk_get_all() API to get the clocks
from Devicetree
.../devicetree/bindings/pci/qcom,pcie.yaml | 37 ++++
.../phy/qcom,ipq8074-qmp-pcie-phy.yaml | 1 +
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 178 +++++++++++++++++-
drivers/clk/qcom/gcc-ipq9574.c | 76 ++++++++
drivers/pci/controller/dwc/pcie-qcom.c | 164 +++-------------
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 136 ++++++++++++-
.../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 14 ++
include/dt-bindings/clock/qcom,ipq9574-gcc.h | 4 +
8 files changed, 469 insertions(+), 141 deletions(-)
