[...]
>>> EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_eq_settings);
>>> +void qcom_pcie_common_set_16gt_rx_margining_settings(struct dw_pcie *pci)
>>> +{
>>> + u32 reg;
>>> +
>>> + reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_1_OFF);
>>> + reg = MARGINING_MAX_VOLTAGE_OFFSET(0x24) |
>>> + MARGINING_NUM_VOLTAGE_STEPS(0x78) |
>>> + MARGINING_MAX_TIMING_OFFSET(0x32) |
>>> + MARGINING_NUM_TIMING_STEPS(0x10);
>>> + dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_1_OFF, reg);
>>
>> Since this is DW-common, why is this inside the qcom driver?
> Though this register space is in dw-common specific, these settings are purely vendor specific . These settings are determined by systems team on vendor hardware, as these settings are used as margin to compensate signal variance due to various physical factors(like connection length, retimers etc).
Okay, so:
1. is the register layout vendor-specific too? i.e. are the bitfields DW-common?
2. will these settings work on all Qualcomm devices, regardless of SoC/board/
retimers used etc.?
Konrad
