Dave Jiang wrote: > Per CXL spec r3.1 8.1.5.2, Secondary Bus Reset (SBR) is masked unless the > "Unmask SBR" bit is set. Add a check to the PCI secondary bus reset > path to fail the CXL SBR request if the "Unmask SBR" bit is clear in > the CXL Port Control Extensions register by returning -ENOTTY. > > When the "Unmask SBR" bit is set to 0 (default), the bus_reset would Feels like a missing "Otherwise," at the beginning of this sentence to indicate transition from what the patch does to what happens without the patch. > appear to have executed successfully. However the operation is actually > masked. The intention is to inform the user that SBR for the CXL device > is masked and will not go through. > > If the "Unmask SBR" bit is set to 1, then the bus reset will execute > successfully. Otherwise, heh heh heh, you can add: Reviewed-by: Dan Williams <dan.j.williams@xxxxxxxxx> ...I would say, do not spin the patch just for that small fixup.
