Martin Mareš wrote:
[..]
>
> This really is not the right place to read from sysfs. The libpci
> should provide a backend-indepenent interface for reading this
> information and the sysfs back-end (lib/sysfs.c) should provide one implementation of this interface.
>
> I think that we can easily extend pci_fill_info() and add another
> PCI_FILL_xxx flag for CXL RCD properties, which will be available in
> struct pci_dev (beware that new fields have to be added _after_ all public fields to keep ABI compatibility).
>
Thank you for your feedback.
I understand that lib/sysfs.c is the appropriate location.
I also understand that to extend it, I need to add code in pci_fill_info()
to read the sysfs file and add a new flag at the bottom of PCI_FILL_xx.
Thank you for the clarification. I will update this in the next patch and
submit it separately from the driver implementation.
Dan Williams wrote:
> Martin Mareš wrote:
> > Hello!
> >
> > > > Does it make sense to look up CXL RCD information for all PCIe devices
> of type
> > > > PCI_EXP_TYPE_ROOT_INT_EP? Shouldn't it be done only for devices
> with the CXL
> > > > capability?
> > >
> > > I think so, would this fit more naturally in pci_scan_caps() with a new
> > > scan for DVSEC caps ("PCI_EXT_CAP_ID_DVSEC" in Linux). However,
> isn't
> > > the trouble that this needs a DVSEC scan for CXL to know it needs to go
> > > back and fill in details that normally in appear in the base PCIe
> > > capability scan?
> >
> > I would prefer to display all CXL stuff together (i.e., when showing the
> > DVSEC caps). Is there any reason not to?
>
> Together with the DVSEC caps display makes sense to me as well.
Here is my understanding of this point. Please let me know if there is a more appropriate approach.
Based on my understanding, the information we are trying to display
with this feature is included in the PCIe Capability. Therefore, I believe
it is appropriate to display it within the cap_express() function. By checking the DVSEC,
we can determine whether this device is a CXL device or not. However,
I couldn't find a proper way to check the DVSEC within the cap_express() function.
As a result, I explored other options and set the PCI_EXP_TYPE_ROOT_INT_EP
as a branching condition.(cxl3.0 specification 7.3.1.2, 9.10)
Furthermore, since rcd is identified as PCI_EXP_TYPE_ROOT_INT_EP by
PCI_EXP_FLAGS_TYPE, cap_express_link() is not called.
Alternatively, I might be able to create a new rcd variable for pci_fill_info()
in struct pci_dev and make it a branch condition.
