Re: [PATCH v3 3/3] Add function to display cxl1.1 device link status

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Hello!

> This patch adds a function to output the link status of the CXL1.1 device
> when it is connected.
> 
> In CXL1.1, the link status of the device is included in the RCRB mapped to
> the memory mapped register area. The value of that register is outputted
> to sysfs, and based on that, displays the link status information.

> diff --git a/lib/access.c b/lib/access.c
> index 7d66123..bc75a84 100644
> --- a/lib/access.c
> +++ b/lib/access.c
[...]
> @@ -268,3 +269,31 @@ pci_get_string_property(struct pci_dev *d, u32 prop)
>  
>    return NULL;
>  }
> +
> +#define OBJNAMELEN 1024
> +#define OBJBUFSIZE 64
> +int
> +get_rcd_sysfs_obj_file(struct pci_dev *d, char *object, char *result)
> +{
> +#ifdef PCI_HAVE_PM_LINUX_SYSFS
> +  char namebuf[OBJNAMELEN];
> +  int n = snprintf(namebuf, OBJNAMELEN, "%s/devices/%04x:%02x:%02x.%d/%s",
> +		   pci_get_param(d->access, "sysfs.path"),
> +       d->domain, d->bus, d->dev, d->func, object);
> +  if (n < 0 || n >= OBJNAMELEN){
> +    d->access->error("Failed to get filename");
> +    return -1;
> +    }
> +  int fd = open(namebuf, O_RDONLY);
> +  if(fd < 0)
> +    return -1;
> +  n = read(fd, result, OBJBUFSIZE);
> +  if (n < 0 || n >= OBJBUFSIZE){
> +    d->access->error("Failed to read the file");
> +    return -1;
> +  }
> +  return 0;
> +#else
> +  return -1;
> +#endif
> +}

This really is not the right place to read from sysfs. The libpci should provide
a backend-indepenent interface for reading this information and the sysfs
back-end (lib/sysfs.c) should provide one implementation of this interface.

I think that we can easily extend pci_fill_info() and add another PCI_FILL_xxx
flag for CXL RCD properties, which will be available in struct pci_dev (beware
that new fields have to be added _after_ all public fields to keep ABI compatibility).

> @@ -1445,6 +1515,9 @@ cap_express(struct device *d, int where, int cap)
>    cap_express_dev(d, where, type);
>    if (link)
>      cap_express_link(d, where, type);
> +  else if (type == PCI_EXP_TYPE_ROOT_INT_EP)
> +    cap_express_link_rcd(d);
> +   
>    if (slot)
>      cap_express_slot(d, where);
>    if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC)

Does it make sense to look up CXL RCD information for all PCIe devices of type
PCI_EXP_TYPE_ROOT_INT_EP? Shouldn't it be done only for devices with the CXL
capability?

				Have a nice fortnight
-- 
Martin `MJ' Mareš                        <mj@xxxxxx>   http://mj.ucw.cz/
United Computer Wizards, Prague, Czech Republic, Europe, Earth, Universe




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