On Wed, Mar 06, 2024 at 10:48:30AM +0200, Dmitry Baryshkov wrote: > On Wed, 6 Mar 2024 at 10:39, Manivannan Sadhasivam > <manivannan.sadhasivam@xxxxxxxxxx> wrote: > > > > On Wed, Mar 06, 2024 at 08:20:16AM +0100, Johan Hovold wrote: > > > On Wed, Mar 06, 2024 at 12:03:02PM +0530, Manivannan Sadhasivam wrote: > > > > On Tue, Mar 05, 2024 at 09:10:55AM +0100, Johan Hovold wrote: > > > > > This series addresses a few problems with the sc8280xp PCIe > > > > > implementation. > > > > > > > > > > The DWC PCIe controller can either use its internal MSI controller or an > > > > > external one such as the GICv3 ITS. Enabling the latter allows for > > > > > assigning affinity to individual interrupts, but results in a large > > > > > amount of Correctable Errors being logged on both the Lenovo ThinkPad > > > > > X13s and the sc8280xp-crd reference design. > > > > > > > > > > It turns out that these errors are always generated, but for some yet to > > > > > be determined reason, the AER interrupts are never received when using > > > > > the internal MSI controller, which makes the link errors harder to > > > > > notice. > > > > > > > > Enabling AER error reporting on sc8280xp could similarly also reveal > > > > > existing problems with the related sa8295p and sa8540p platforms as they > > > > > share the base dtsi. > > > > > > > > > > After discussing this with Bjorn Andersson at Qualcomm we have decided > > > > > to go ahead and disable L0s for all controllers on the CRD and the > > > > > X13s. > > > > > > > Just received confirmation from Qcom that L0s is not supported for any of the > > > > PCIe instances in sc8280xp (and its derivatives). Please move the property to > > > > SoC dtsi. > > > > > > Ok, thanks for confirming. But then the devicetree property is not the > > > right way to handle this, and we should disable L0s based on the > > > compatible string instead. > > > > > > > Hmm. I checked further and got the info that there is no change in the IP, but > > the PHY sequence is not tuned correctly for L0s (as I suspected earlier). So > > there will be AERs when L0s is enabled on any controller instance. And there > > will be no updated PHY sequence in the future also for this chipset. > > Why? If it is a bug in the PHY driver, it should be fixed there > instead of adding workarounds. > Fixing the L0s support requires the expertise of the PHY team and they will only do if there is any real demand (like in the case of mobile chipsets). For compute chipsets, they didn't do because most of the NVMe devices out there in the market only support L1 and L1ss. So we have to live with this limitation for now. - Mani > > > > So yeah, let's disable it in the driver instead. > > > > > > > As we are now at 6.8-rc7, I've rebased this series on the Qualcomm PCIe > > > > > binding rework in linux-next so that the whole series can be merged for > > > > > 6.9 (the 'aspm-no-l0s' support and devicetree fixes are all marked for > > > > > stable backport anyway). > > > > > > I'll respin the series. Looks like we've already missed the chance to > > > enable ITS in 6.9 anyway. > > > > > > > Sounds good, thanks! > > > > - Mani > > > > -- > > மணிவண்ணன் சதாசிவம் > > > > > -- > With best wishes > Dmitry -- மணிவண்ணன் சதாசிவம்
