The Controller driver is the parent device of the PCIe host bridge, PCI-PCI bridge and PCIe endpoint as shown below. PCIe controller(Top level parent & parent of host bridge) | v PCIe Host bridge(Parent of PCI-PCI bridge) | v PCI-PCI bridge(Parent of endpoint driver) | v PCIe endpoint driver Since runtime PM is disabled for host bridge, the state of the child devices under the host bridge is not taken into account by PM framework for the top level parent, PCIe controller. So PM framework, allows the controller driver to enter runtime PM irrespective of the state of the devices under the host bridge. And this causes the topology breakage and also possible PM issues. So enable pm runtime for the host bridge, so that controller driver goes to suspend only when all child devices goes to runtime suspend. Signed-off-by: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx> --- Changes in v2: - Updated commit message as suggested by mani. - Link to v1: https://lore.kernel.org/r/20240219-runtime_pm_enable-v1-1-d39660310504@xxxxxxxxxxx --- drivers/pci/controller/dwc/pcie-designware-host.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index d5fc31f8345f..57756a73df30 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -16,6 +16,7 @@ #include <linux/of_pci.h> #include <linux/pci_regs.h> #include <linux/platform_device.h> +#include <linux/pm_runtime.h> #include "../../pci.h" #include "pcie-designware.h" @@ -505,6 +506,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (pp->ops->post_init) pp->ops->post_init(pp); + pm_runtime_set_active(&bridge->dev); + pm_runtime_enable(&bridge->dev); + return 0; err_stop_link: --- base-commit: 6613476e225e090cc9aad49be7fa504e290dd33d change-id: 20240219-runtime_pm_enable-bdc17914bd50 Best regards, -- Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx>
