On Mar 04, 2024 / 12:04, Hans de Goede wrote: ... > So the p2sb_bar(devfn=0) call actually only happens on Goldmont from: > > 3) mfd/lpc_ich for pinctrl devfn = 0 > > and then only when the ACPI tables fail to properly describe the GPIO > controllers as ACPI devices, if the GPIO controllers are described > in ACPI, which they are on the ASUS VivoBook D540NV-GQ065T then that > call gets skipped. > > So on the ASUS VivoBook D540NV-GQ065T p2sb_bar(devfn=0) gets never > called. Which explains why not caching it fixes things. I assume that this > laptop just seems not likes the P2SB is touched at all and by not caching > the BAR for the P2SB it ends up not getting touched at all. Thanks for sharing the insights. > > This also means that likely the P2SB devfn itself generally speaking is > often not touched on Goldmont platforms. So we can avoid the lockdep > issue on PCI bus rescan there by caching the SPI controller > PCI_DEVFN(13, 2) devfn from fs_initcall(), since that will be the only > devfn for which p2sb_bar() will get called (except on hw with the > GPIO controller missing from the ACPI tables which should be rare). Oh, this sounds a great idea. > > I have prepared a follow up patch to your v3 to cache the > SPI controller devfn instead of the P2SB devfn at fs_initcall() > time. I'll post this shortly and I'll also ask the bug reporter > to test the combination of our 2 patches. Thanks a lot. Looking forward to the results.
