On Thu, Feb 08, 2024 at 07:12:47PM +0000, Conor Dooley wrote: > On Wed, Feb 07, 2024 at 12:49:19PM -0500, Frank Li wrote: > > On Wed, Feb 07, 2024 at 05:17:55PM +0000, Conor Dooley wrote: > > > Hey Frank, > > > > > > On Wed, Feb 07, 2024 at 01:24:02AM -0500, Frank Li wrote: > > > > Convert layerscape pcie bind document to yaml file. > > > > > > > > Signed-off-by: Frank Li <Frank.Li@xxxxxxx> > > > > --- > > > > .../bindings/pci/fsl,layerscape-pcie-ep.yaml | 84 +++++++++ > > > > .../bindings/pci/fsl,layerscape-pcie.yaml | 163 ++++++++++++++++++ > > > > .../bindings/pci/layerscape-pci.txt | 79 --------- > > > > 3 files changed, 247 insertions(+), 79 deletions(-) > > > > create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml > > > > create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml > > > > delete mode 100644 Documentation/devicetree/bindings/pci/layerscape-pci.txt > > > > > > > > diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml > > > > new file mode 100644 > > > > index 0000000000000..3b592c820eb4c > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml > > > > @@ -0,0 +1,84 @@ > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > > +%YAML 1.2 > > > > +--- > > > > +$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie-ep.yaml# > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > + > > > > +title: Freescale Layerscape PCIe controller > > > > + > > > > +maintainers: > > > > + - Frank Li <Frank.Li@xxxxxxx> > > > > + > > > > +description: |+ > > > > > > Are you sure that you need this chomping operator? > > > > > > > + This PCIe endpoint controller is based on the Synopsys DesignWare PCIe IP > > > > > > > + and thus inherits all the common properties defined in snps,dw-pcie-ep.yaml. > > > > > > You shouldn't need this statement given you have the ref: below. > > > > > > > + > > > > + This controller derives its clocks from the Reset Configuration Word (RCW) > > > > + which is used to describe the PLL settings at the time of chip-reset. > > > > + > > > > + Also as per the available Reference Manuals, there is no specific 'version' > > > > + register available in the Freescale PCIe controller register set, > > > > + which can allow determining the underlying DesignWare PCIe controller version > > > > + information. > > > > + > > > > +properties: > > > > + compatible: > > > > + enum: > > > > + - fsl,ls2088a-pcie-ep > > > > + - fsl,ls1088a-pcie-ep > > > > + - fsl,ls1046a-pcie-ep > > > > + - fsl,ls1028a-pcie-ep > > > > + - fsl,lx2160ar2-pcie-ep > > > > > > Where did the fallback compatible go? > > > > So far, no fallback compatible needed now. each devices already have its > > compatible string. > > It used to exist though, have you checked that u-boot or *bsd etc do not > use the fallback compatible? You also need to mention your justification > for removing it in the commit message. This commit just convert binding doc from txt to yaml. I just make sure which equal to what descript in txt. If there are someting wrong in "uboot" or "bsd", we can fixed it later. I checked driver code. exited dts tree under kernel, which use unexited fallback compatible string "fsl, lx-pcie-ep", which should be removed at dts file. > > > > > + > > > > + reg: > > > > + maxItems: 2 > > > > + > > > > + reg-names: > > > > + items: > > > > + - const: regs > > > > + - const: addr_space > > > > > > The example uses "regs" and "config". Where did addr_space come from? > > > > Example just show pcie-host part. Not show pcie-ep part. > > pcie-ep part need 'addr_space'. > > Okay. Again, please mention where this is coming from. Ideally it comes from snsp,dwc-pcie-ep.yaml. but it is use 'dbi' instead of 'regs'. It needs extra effort to make driver code algin common snps,dwc-pcie-ep.yaml, and update exist all dts files. I think it will be deleted soon. > > > > > > > > > > + fsl,pcie-scfg: > > > > + $ref: /schemas/types.yaml#/definitions/phandle > > > > + description: A phandle to the SCFG device node. The second entry is the > > > > + physical PCIe controller index starting from '0'. This is used to get > > > > + SCFG PEXN registers. > > > > + > > > > + dma-coherent: > > > > > > dma-coherent: true > > > > > > > + $ref: /schemas/types.yaml#/definitions/flag > > > > + description: Indicates that the hardware IP block can ensure the coherency > > > > + of the data transferred from/to the IP block. This can avoid the software > > > > + cache flush/invalid actions, and improve the performance significantly. > > > > + > > > > + big-endian: > > > > + $ref: /schemas/types.yaml#/definitions/flag > > > > + description: If the PEX_LUT and PF register block is in big-endian, specify > > > > + this property. > > > > + > > > > +required: > > > > + - compatible > > > > + - reg > > > > + - reg-names > > > > > > This was not previously required, why is it required now? > > > > Actually its needed. > > Well, if it wasn't, I'd hope that you wouldn't be making it required. > But I asked /why/ and you've not given a reason. Please mention the why > in your commit message for v2. Sorry, I just sent v2 before see this. According to driver code, it is needed. Please check v2, I will update at v3. > > Cheers, > Conor. >
