Hey Frank, On Wed, Feb 07, 2024 at 01:24:02AM -0500, Frank Li wrote: > Convert layerscape pcie bind document to yaml file. > > Signed-off-by: Frank Li <Frank.Li@xxxxxxx> > --- > .../bindings/pci/fsl,layerscape-pcie-ep.yaml | 84 +++++++++ > .../bindings/pci/fsl,layerscape-pcie.yaml | 163 ++++++++++++++++++ > .../bindings/pci/layerscape-pci.txt | 79 --------- > 3 files changed, 247 insertions(+), 79 deletions(-) > create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml > create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml > delete mode 100644 Documentation/devicetree/bindings/pci/layerscape-pci.txt > > diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml > new file mode 100644 > index 0000000000000..3b592c820eb4c > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml > @@ -0,0 +1,84 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie-ep.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Freescale Layerscape PCIe controller > + > +maintainers: > + - Frank Li <Frank.Li@xxxxxxx> > + > +description: |+ Are you sure that you need this chomping operator? > + This PCIe endpoint controller is based on the Synopsys DesignWare PCIe IP > + and thus inherits all the common properties defined in snps,dw-pcie-ep.yaml. You shouldn't need this statement given you have the ref: below. > + > + This controller derives its clocks from the Reset Configuration Word (RCW) > + which is used to describe the PLL settings at the time of chip-reset. > + > + Also as per the available Reference Manuals, there is no specific 'version' > + register available in the Freescale PCIe controller register set, > + which can allow determining the underlying DesignWare PCIe controller version > + information. > + > +properties: > + compatible: > + enum: > + - fsl,ls2088a-pcie-ep > + - fsl,ls1088a-pcie-ep > + - fsl,ls1046a-pcie-ep > + - fsl,ls1028a-pcie-ep > + - fsl,lx2160ar2-pcie-ep Where did the fallback compatible go? > + > + reg: > + maxItems: 2 > + > + reg-names: > + items: > + - const: regs > + - const: addr_space The example uses "regs" and "config". Where did addr_space come from? > + fsl,pcie-scfg: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: A phandle to the SCFG device node. The second entry is the > + physical PCIe controller index starting from '0'. This is used to get > + SCFG PEXN registers. > + > + dma-coherent: dma-coherent: true > + $ref: /schemas/types.yaml#/definitions/flag > + description: Indicates that the hardware IP block can ensure the coherency > + of the data transferred from/to the IP block. This can avoid the software > + cache flush/invalid actions, and improve the performance significantly. > + > + big-endian: > + $ref: /schemas/types.yaml#/definitions/flag > + description: If the PEX_LUT and PF register block is in big-endian, specify > + this property. > + > +required: > + - compatible > + - reg > + - reg-names This was not previously required, why is it required now? > + - "#address-cells" > + - "#size-cells" > + - device_type > + - bus-range > + - ranges > + > +allOf: > + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# > + > + - if: > + properties: > + compatible: > + enum: > + - fsl,ls1028a-pcie-ep > + - fsl,ls1046a-pcie-ep > + - fsl,ls1088a-pcie-ep > + then: > + properties: > + interrupt-names: > + items: > + - const: pme Please define the interrupt properties at the top-level and constrain them on a per-device basis. > + > +unevaluatedProperties: false > diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml > new file mode 100644 > index 0000000000000..e3719da306f25 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml > @@ -0,0 +1,163 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# Only brief comments here, as it most is the same comments as for the > + > +title: Freescale Layerscape PCIe controller > + > +maintainers: > + - Frank Li <Frank.Li@xxxxxxx> > + > +description: |+ > + This PCIe host controller is based on the Synopsys DesignWare PCIe IP > + and thus inherits all the common properties defined in snps,dw-pcie.yaml. Same two comments here as above. > + > + This controller derives its clocks from the Reset Configuration Word (RCW) > + which is used to describe the PLL settings at the time of chip-reset. > + > + Also as per the available Reference Manuals, there is no specific 'version' > + register available in the Freescale PCIe controller register set, > + which can allow determining the underlying DesignWare PCIe controller version > + information. > + > +properties: > + compatible: > + enum: > + - fsl,ls1021a-pcie > + - fsl,ls2080a-pcie > + - fsl,ls2085a-pcie > + - fsl,ls2088a-pcie > + - fsl,ls1088a-pcie > + - fsl,ls1046a-pcie > + - fsl,ls1043a-pcie > + - fsl,ls1012a-pcie > + - fsl,ls1028a-pcie > + > + reg: > + maxItems: 2 > + > + reg-names: > + items: > + - const: regs > + - const: config > + > + fsl,pcie-scfg: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: A phandle to the SCFG device node. The second entry is the > + physical PCIe controller index starting from '0'. This is used to get > + SCFG PEXN registers. > + > + dma-coherent: > + $ref: /schemas/types.yaml#/definitions/flag > + description: Indicates that the hardware IP block can ensure the coherency > + of the data transferred from/to the IP block. This can avoid the software > + cache flush/invalid actions, and improve the performance significantly. Same here. > + > + big-endian: > + $ref: /schemas/types.yaml#/definitions/flag > + description: If the PEX_LUT and PF register block is in big-endian, specify > + this property. > + > + msi-parent: true > + > + iommu-map: true > + > +required: > + - compatible > + - reg > + - reg-names Same here. > + - "#address-cells" > + - "#size-cells" > + - device_type > + - bus-range > + - ranges > + - interrupts > + - interrupt-names > + - "#interrupt-cells" > + - interrupt-map-mask > + - interrupt-map > + > +allOf: > + - $ref: /schemas/pci/pci-bus.yaml# > + > + - if: > + properties: > + compatible: > + enum: > + - fsl,ls1028a-pcie > + - fsl,ls1046a-pcie > + - fsl,ls1043a-pcie > + - fsl,ls1012a-pcie > + then: > + properties: > + interrupts: > + maxItems: 2 > + interrupt-names: > + items: > + - const: pme > + - const: aer > + > + - if: > + properties: > + compatible: > + enum: > + - fsl,ls2080a-pcie > + - fsl,ls2085a-pcie > + - fsl,ls2088a-pcie > + then: > + properties: > + interrupts: > + maxItems: 1 > + interrupt-names: > + items: > + - const: intr > + > + - if: > + properties: > + compatible: > + enum: > + - fsl,ls1088a-pcie > + then: > + properties: > + interrupts: > + maxItems: 1 > + interrupt-names: > + items: > + - const: aer And same here. Thanks, Conor.
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