On 2023/11/30 7:22, Bjorn Helgaas wrote: > On Fri, Nov 24, 2023 at 09:45:08AM +0800, Kevin Xie wrote: >> Add the PCIE_CONFIG_REQUEST_WAIT_MS marco to define the minimum waiting >> time between sending the first configuration request to the device and >> exit from a conventional reset (or after link training completes). >> >> As described in the conventional reset rules of PCI specifications, >> there are two different use cases of the value: >> >> - With a downstream port that supports link speeds <= 5.0 GT/s, >> the waiting is following exit from a conventional reset. >> >> - With a downstream port that supports link speeds > 5.0 GT/s, >> the waiting is after link training completes. >> >> Signed-off-by: Kevin Xie <kevin.xie@xxxxxxxxxxxxxxxx> >> Reviewed-by: Mason Huo <mason.huo@xxxxxxxxxxxxxxxx> >> --- >> drivers/pci/pci.h | 7 +++++++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h >> index 5ecbcf041179..4ca8766e546e 100644 >> --- a/drivers/pci/pci.h >> +++ b/drivers/pci/pci.h >> @@ -22,6 +22,13 @@ >> */ >> #define PCIE_PME_TO_L2_TIMEOUT_US 10000 >> >> +/* >> + * PCIe r6.0, sec 6.6.1, <Conventional Reset> >> + * Requires a minimum waiting of 100ms before sending a configuration >> + * request to the device. >> + */ >> +#define PCIE_CONFIG_REQUEST_WAIT_MS 100 > > Oh, and I think this name should include something about "reset" > because that's the common scenario and that's the spec section where > the value is mentioned. Agree, how about PCIE_RESET_CONFIG_DEVICE_WAIT_MS?
