On Wed, Sep 06, 2023 at 10:59:20PM +0300, Andy Shevchenko wrote:
> On Wed, Sep 06, 2023 at 02:06:23PM -0500, Bjorn Helgaas wrote:
> > On Wed, Aug 16, 2023 at 05:21:15PM +0000, Bartosz Pawlowski wrote:
...
> > > +/*
> > > + * Intel IPU E2000 revisions before C0 implement incorrect endianness
> > > + * in ATS Invalidate Request message body. Although there is existing software
> > > + * workaround for this issue, it is not functionally complete (no 5-lvl paging
> > > + * support) and it requires changes in all IOMMU implementations supporting
> > > + * ATS. Therefore, disabling ATS seems to be more reasonable.
> >
> > Can we reference the commit that added the existing software
> > workaround?
> See below.
Oh, I meant the second question here, i.e.
> > It sounds like systems that (a) don't require 5-level paging and (b)
> > use an IOMMU implementation that include the appropriate changes might
> > still be able to use ATS? Is there a way for them to do that?
^^^ this one.
> > > + */
> > > +static void quirk_intel_e2000_no_ats(struct pci_dev *pdev)
> > > +{
>
> > > + if (pdev->revision < 0x20)
>
> Isn't it the answer to your question?
>
> > > + quirk_no_ats(pdev);
> > > +}
--
With Best Regards,
Andy Shevchenko
