On Wed, Aug 16, 2023 at 05:21:15PM +0000, Bartosz Pawlowski wrote:
> There is a HW issue in A and B steppings of Intel IPU E2000 that it
> expects wrong endianness in ATS invalidation message body. This problem
> can lead to outdated translations being returned as valid and finally
> cause system instability.
Is there a published erratum for this? Or at least a number to
identify it?
> In order to prevent such issues introduce quirk_intel_e2000_no_ats()
> function to disable ATS for vulnerable IPU E2000 devices.
>
> Signed-off-by: Bartosz Pawlowski <bartosz.pawlowski@xxxxxxxxx>
> Reviewed-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
> Reviewed-by: Alexander Lobakin <aleksander.lobakin@xxxxxxxxx>
> ---
> drivers/pci/quirks.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index a900546d8d45..9aa1e0148ed2 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -5550,6 +5550,28 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats);
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats);
> /* AMD Raven platform iGPU */
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats);
> +
> +/*
> + * Intel IPU E2000 revisions before C0 implement incorrect endianness
> + * in ATS Invalidate Request message body. Although there is existing software
> + * workaround for this issue, it is not functionally complete (no 5-lvl paging
> + * support) and it requires changes in all IOMMU implementations supporting
> + * ATS. Therefore, disabling ATS seems to be more reasonable.
Can we reference the commit that added the existing software
workaround?
It sounds like systems that (a) don't require 5-level paging and (b)
use an IOMMU implementation that include the appropriate changes might
still be able to use ATS? Is there a way for them to do that?
> + */
> +static void quirk_intel_e2000_no_ats(struct pci_dev *pdev)
> +{
> + if (pdev->revision < 0x20)
> + quirk_no_ats(pdev);
> +}
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1451, quirk_intel_e2000_no_ats);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1452, quirk_intel_e2000_no_ats);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1453, quirk_intel_e2000_no_ats);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1454, quirk_intel_e2000_no_ats);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1455, quirk_intel_e2000_no_ats);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats);
> #endif /* CONFIG_PCI_ATS */
>
> /* Freescale PCIe doesn't support MSI in RC mode */
> --
> 2.41.0
>
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