On Wed, Jul 12, 2023 at 12:17:47AM +0000, Yoshihiro Shimoda wrote:
> Hello Serge,
>
> > From: Serge Semin, Sent: Wednesday, July 12, 2023 6:03 AM
> >
> > On Wed, Jul 05, 2023 at 08:42:02PM +0900, Yoshihiro Shimoda wrote:
> > > Document bindings for Renesas R-Car Gen4 and R-Car S4-8 (R8A779F0)
> > > PCIe endpoint module.
> > >
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> > > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
> > > Reviewed-by: Serge Semin <fancer.lancer@xxxxxxxxx>
> > > Acked-by: Manivannan Sadhasivam <mani@xxxxxxxxxx>
> > > ---
> > > .../bindings/pci/rcar-gen4-pci-ep.yaml | 106 ++++++++++++++++++
> > > 1 file changed, 106 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
> > b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
> > > new file mode 100644
> > > index 000000000000..4e6be856104c
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
> > > @@ -0,0 +1,106 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +# Copyright (C) 2022-2023 Renesas Electronics Corp.
> > > +%YAML 1.2
> > > +---
> > > +$id:
> <snip URL>
> > > +$schema:
> <snip URL>
> > > +
> > > +title: Renesas R-Car Gen4 PCIe Endpoint
> > > +
> > > +maintainers:
> > > + - Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> > > +
> > > +allOf:
> > > + - $ref: snps,dw-pcie-ep.yaml#
> > > +
> > > +properties:
> > > + compatible:
> > > + items:
> > > + - const: renesas,r8a779f0-pcie-ep # R-Car S4-8
> > > + - const: renesas,rcar-gen4-pcie-ep # R-Car Gen4
> > > +
> > > + reg:
> > > + maxItems: 6
> > > +
> > > + reg-names:
> > > + items:
> > > + - const: dbi
> > > + - const: dbi2
> > > + - const: atu
> > > + - const: dma
> > > + - const: app
> > > + - const: addr_space
> > > +
> > > + interrupts:
> > > + maxItems: 3
> > > +
> > > + interrupt-names:
> > > + items:
> > > + - const: dma
> > > + - const: sft_ce
> > > + - const: app
> > > +
> > > + power-domains:
> > > + maxItems: 1
> > > +
> > > + resets:
> > > + maxItems: 1
> > > +
> > > + clocks:
> > > + maxItems: 2
> > > +
> > > + clock-names:
> > > + items:
> > > + - const: core
> > > + - const: ref
> > > +
> > > + max-functions:
> > > + maximum: 2
> > > +
> > > + max-link-speed:
> > > + maximum: 4
> > > +
> > > + num-lanes:
> > > + maximum: 4
> > > +
> > > +required:
> > > + - compatible
> > > + - reg
> > > + - reg-names
> > > + - interrupts
> > > + - resets
> > > + - power-domains
> > > + - clocks
> > > + - clock-names
> > > +
> > > +unevaluatedProperties: false
> > > +
> > > +examples:
> > > + - |
> > > + #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
> > > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > + #include <dt-bindings/power/r8a779f0-sysc.h>
> > > +
> > > + soc {
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > +
> > > + pcie0_ep: pcie-ep@e65d0000 {
> > > + compatible = "renesas,r8a779f0-pcie-ep", "renesas,rcar-gen4-pcie-ep";
> >
> > > + reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2800 0 0x0800>,
> > > + <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
> > > + <0 0xe65d6200 0 0x0e00>, <0 0xfe000000 0 0x400000>;
> > > + reg-names = "dbi", "dbi2", "atu", "dma", "app", "addr_space";
> >
> > I'll ask it once again since you didn't address my comment in v16 and
> > haven't fixed the example node in the bindings:
>
> Thank you for your review! I'm sorry, I completely forgot about this...
>
> > I see you defining the dbi2 space as <0 _0xe65d2800_ 0 0x0800>. But
> > sometime before you mentioned that your device has the next CSRs
> > layout:
> > ! +0x0000 : Function 0 (common address in Root port and Endpoint mode)
> > +0x1000 : Function 1 (Endpoint mode only)
> > +0x2000 : Shadow register for Function 0
> > ! +0x2800 : Shadow register for Function 1
> > it means the DT-bindings example node has the dbi space defined for
> > both functions meanwhile the dbi2 space defined for _function #1_ only
> > (it's 0xe65d0000 + 0x2800). So AFAICS either you have wrong space
> > defined in the example node or the node is wrong in your platform DTS
> > too and you have a malfunction end-point mode. Am I missing something?
> > In any case based on your End-point driver implementation dbi2 is
> > supposed to be defined at the 0xe65d2000 base address.
> >
> > Am I wrong? Could you clarify this?
>
> You're correct. So, I had investigated this topic, and then the current
> actual dtsi file has the following about the reg property:
>
> + reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,
> + <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
> + <0 0xe65d6200 0 0x0e00>, <0 0xfe000000 0 0x400000>;
>
> After that, the driver could not work correctly on v16 patch series.
> So, I had investigated why, and then I found this was related to
> the dbi2 offset. That's why I added a new patch [1] on v17 patch series.
>
> [1] "[PATCH v17 07/20] PCI: dwc: endpoint: Add multiple PFs support for dbi2"
>
> Anyway, I'll revise this dt-bindings doc too on v18 patch series.
Got it. Thanks for clarification.
-Serge(y)
>
> Best regards,
> Yoshihiro Shimoda
>
> > -Serge(y)
> >
> > > + interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
> > > + interrupt-names = "dma", "sft_ce", "app";
> > > + clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
> > > + clock-names = "core", "ref";
> > > + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
> > > + resets = <&cpg 624>;
> > > + num-lanes = <2>;
> > > + max-link-speed = <4>;
> > > + max-functions = /bits/ 8 <2>;
> > > + };
> > > + };
> > > --
> > > 2.25.1
> > >
