On Tue, May 30, 2023 at 09:17:02PM +0000, Matthias Kaehlcke wrote: > On Mon, May 29, 2023 at 10:18:56PM +0530, Manivannan Sadhasivam wrote: > > On Thu, May 25, 2023 at 04:35:12PM +0800, Owen Yang wrote: > > > Implement this workaround until Qualcomm fixed the > > > correct NVMe suspend process. > > > > > > Signed-off-by: Owen Yang <ecs.taipeikernel@xxxxxxxxx> > > > --- > > > > > > drivers/pci/quirks.c | 10 ++++++++++ > > > 1 file changed, 10 insertions(+) > > > > > > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c > > > index f4e2a88729fd..b57876dc2624 100644 > > > --- a/drivers/pci/quirks.c > > > +++ b/drivers/pci/quirks.c > > > @@ -5945,6 +5945,16 @@ static void nvidia_ion_ahci_fixup(struct pci_dev *pdev) > > > } > > > DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup); > > > > > > +/* In Qualcomm 7c gen 3 sc7280 platform. Some of the SSD won't enter > > > + * the correct ASPM state properly. Therefore. Implement this workaround > > > + * until Qualcomm fixed the correct NVMe suspend process*/ > > > > What is there to fix during suspend? Currently, Qcom PCIe driver just votes for > > low interconnect bandwidth and keeps the resources (clocks, regulators) ON > > during suspend. So there is no way the device would move to D3Cold. > > > > Earlier Qcom reported that during suspend, link down event happens when the > > resources are turned OFF without waiting for the link to enter L1ss. But as I > > said above, we are _not_ turning OFF any resources. > > Right, it makes little sense that the NVMe would move to D3Cold. And why does > the issue only reproduces sometimes (with certain NVMes) and not consistently? > Honestly, I don't have any idea why it is happening. The link should transition to L1ss during suspend and we keep all resources ON. Did ECS only observe this issue when ASPM is enabled (powersupersave)? If so, then it is a NVMe firmware issue not Qualcomm. > > I believe this patch is addressing an issue that is caused by an out-of-tree > > patch. > > I think ECS observed this with Chrome OS v5.15 kernel. On the PCI side this > kernel only has backported changes from upstream (mostly clean picks), no > downstream patches, so it seems unlikely that the issue is caused by a > downstream patch. Okay, thanks for the clarification. Is it possible to reproduce it on mainline? Just to rule out the upstream vs downstream difference elsewhere. That should also be the case to submit a patch against mainline. - Mani -- மணிவண்ணன் சதாசிவம்
