On 11/14/2022 09:33, Rafael J. Wysocki wrote:
On Fri, Nov 11, 2022 at 10:42 PM Bjorn Helgaas <helgaas@xxxxxxxxxx> wrote:
On Fri, Nov 11, 2022 at 12:58:28PM -0600, Limonciello, Mario wrote:
On 11/11/2022 11:41, Bjorn Helgaas wrote:
On Mon, Oct 31, 2022 at 05:33:55PM -0500, Mario Limonciello wrote:
Firmware typically advertises that ACPI devices that represent PCIe
devices can support D3 by a combination of the value returned by
_S0W as well as the HotPlugSupportInD3 _DSD [1].
`acpi_pci_bridge_d3` looks for this combination but also contains
an assumption that if an ACPI device contains power resources the PCIe
device it's associated with can support D3. This was introduced
from commit c6e331312ebf ("PCI/ACPI: Whitelist hotplug ports for
D3 if power managed by ACPI").
Some firmware configurations for "AMD Pink Sardine" do not support
wake from D3 in _S0W for the ACPI device representing the PCIe root
port used for tunneling. The PCIe device will still be opted into
runtime PM in the kernel [2] because of the logic within
`acpi_pci_bridge_d3`. This currently happens because the ACPI
device contains power resources.
Wait. Is this as simple as just recognizing that:
_PS0 means the OS has a knob to put the device in D0, but it doesn't
mean the device can wake itself from a low-power state. The OS has
to use _S0W to learn the device's ability to wake itself.
It is.
If that's enough, maybe we don't need to complicate this with all the
Thunderbolt and device link stuff. Which would be great, because the
code change itself has nothing to do with those things.
Indeed.
I'd think it's still useful to leave "something" in the commit message
about how we got to that conclusion though.
Bjorn, do you want me to to attempt to rewrite the commit message and
send a v6, or would you like to?
Thanks,
