On 10/11/2022 13:53, Johan Hovold wrote:
On Thu, Nov 10, 2022 at 01:33:44PM +0300, Dmitry Baryshkov wrote:
Add PCIe0 and PCIe1 (and corresponding PHY) devices found on SM8350
platform. The PCIe0 is a 1-lane Gen3 host, PCIe1 is a 2-lane Gen3 host.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 246 ++++++++++++++++++++++++++-
1 file changed, 244 insertions(+), 2 deletions(-)
@@ -1761,6 +1957,52 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 204>;
wakeup-parent = <&pdc>;
+ pcie0_default_state: pcie0-default-state {
+ perst-pins {
+ pins = "gpio94";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq-pins {
+ pins = "gpio95";
+ function = "pcie0_clkreqn";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake-pins {
+ pins = "gpio96";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
The pinconfig should go in the board file.
Usually yes. However for the PCIe we usually put them into the main
.dtsi. See sm8[124]50.dtsi.
--
With best wishes
Dmitry
