On Tue, Nov 01, 2022 at 09:44:41AM +0100, Lucas Stach wrote: > Hi Shawn, Richard, > > Am Samstag, dem 29.10.2022 um 16:45 +0800 schrieb Shawn Guo: > > On Mon, Oct 24, 2022 at 01:43:09PM +0800, Richard Zhu wrote: > > > Add PCIe SYSPLL configurations, thus the internal SYSPLL can be used as > > > i.MX8MP PCIe reference clock. > > > > > > The following properties of PHY dts node should be changed accordingly. > > > - Set 'fsl,refclk-pad-mode' as '<IMX8_PCIE_REFCLK_PAD_OUTPUT>'. > > > - Change 'clocks' to '<&clk IMX8MP_CLK_HSIO_ROOT>'. > > > > > > Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx> > > > > Applied, thanks! > > Sorry for the late reply, but I'm not really happy with the fact that > the PLL is now unconditionally enabled, even though it is only needed > when there is no external reference clock source. > I fear that this will be hard to correct later on as the DT abstraction > is wrong, as IMX8MP_CLK_HSIO_ROOT is NOT the reference clock for the > PHY, but the PLL generated clock, which isn't properly exposed with > this series. > > I'm not happy to see this going in in the current state and if not too > late would like to ask Shawn to remove it from the tree again. Removed. Shawn
