Hi Matt,
On 20/10/22 6:59 am, Matt Ranostay wrote:
> Add support for setting of two-bit field that allows selection of 4x
> lane PCIe which was previously limited to only 2x lanes.
>
> Signed-off-by: Matt Ranostay <mranostay@xxxxxx>
> ---
> drivers/pci/controller/cadence/pci-j721e.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> index a82f845cc4b5..d9b1527421c3 100644
> --- a/drivers/pci/controller/cadence/pci-j721e.c
> +++ b/drivers/pci/controller/cadence/pci-j721e.c
> @@ -43,7 +43,6 @@ enum link_status {
> };
>
> #define J721E_MODE_RC BIT(7)
> -#define LANE_COUNT_MASK BIT(8)
> #define LANE_COUNT(n) ((n) << 8)
>
> #define GENERATION_SEL_MASK GENMASK(1, 0)
> @@ -207,11 +206,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
> {
> struct device *dev = pcie->cdns_pcie->dev;
> u32 lanes = pcie->num_lanes;
> + u32 mask = GENMASK(8, 8);
> u32 val = 0;
> int ret;
>
> + if (lanes == 4)
> + mask = GENMASK(9, 8);
Shouldn't we decide "mask" based on max_lanes added in 2/3 (ie how many
lanes HW can support and thus width of this bit field) instead of
num_lanes? Hypothetically, what if bootloader / other entity has set MSb
but Linux is restricted to 2 lanes in DT?
> +
> val = LANE_COUNT(lanes - 1);
> - ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val);
> + ret = regmap_update_bits(syscon, offset, mask, val);
> if (ret)
> dev_err(dev, "failed to set link count\n");
>
