On Wed, Aug 31, 2022 at 04:26:31PM -0500, Rob Herring wrote: > On Mon, Aug 22, 2022 at 09:46:54PM +0300, Serge Semin wrote: > > As the DT-bindings description states the Rockchip PCIe controller is > > based on the DW PCIe RP IP-core thus its DT-nodes are supposed to be > > compatible with the common DW PCIe controller schema. Let's make sure they > > are evaluated against it by referring to the snps,dw-pcie.yaml schema in > > the allOf sub-schemas composition. > > > > Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx> > > > > --- > > > > Changelog v3: > > - This is a new patch created on v3 lap of the series. > > > > Changelog v5: > > - Apply snps,dw-pcie.yaml instead of the snps,dw-pcie-common.yaml schema. > > --- > > Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > Shouldn't this come before/after patch 7? It must be applied after the patch [PATCH v5 11/20] dt-bindings: PCI: dwc: Add clocks/resets common properties and after the rest of the resource-related patches submitted before that one. -Sergey > > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
